research-article

WCET-driven cache-aware code positioning

Authors:

Helena KotthausAuthors Info & Claims

CASES '11: Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems

Pages 145 - 154

https://doi.org/10.1145/2038698.2038722

Published: 09 October 2011 Publication History

Abstract

Code positioning is a well-known compiler optimization aiming at the improvement of the instruction cache behavior. A contiguous mapping of code fragments in memory avoids overlapping of cache sets and thus decreases the number of cache conflict misses.

We present a novel cache-aware code positioning optimization driven by worst-case execution time (WCET) information. For this purpose, we introduce a formal cache model based on a conflict graph which is able to capture a broad class of cache architectures. This cache model is combined with a formal WCET timing model, resulting in a cache conflict graph weighted with WCET data. This conflict graph is then exploited by heuristics for code positioning of both basic blocks and entire functions.

Code positioning is able to decrease the accumulated cache misses for a total of 18 real-life benchmarks by 15.5% on average for an automotive processor featuring a 2-way set-associative cache. These cache miss reductions translate to average WCET reductions by 6.1%. For direct-mapped caches, even larger savings of 18.8% (cache misses) and 9.0% (WCET) were achieved.

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Cited By

Milutinovic SMezzetti EAbella JCazorla F(2019)Increasing the Reliability of Software Timing Analysis for Cache-Based ProcessorsIEEE Transactions on Computers10.1109/TC.2018.289062668:6(836-851)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1109/TC.2018.2890626
Kloda TSolieri MMancuso RCapodieci NValente PBertogna M(2019)Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems2019 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)10.1109/RTAS.2019.00009(1-14)Online publication date: Apr-2019
https://doi.org/10.1109/RTAS.2019.00009
Su XWu HXue J(2017)An Efficient WCET-Aware Instruction Scheduling and Register Allocation Approach for Clustered VLIW ProcessorsACM Transactions on Embedded Computing Systems10.1145/312652416:5s(1-21)Online publication date: 27-Sep-2017
https://dl.acm.org/doi/10.1145/3126524
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WCET-driven cache-aware code positioning

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cover image ACM Conferences

CASES '11: Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems

October 2011

250 pages

ISBN:9781450307130

DOI:10.1145/2038698

Program Chairs:
Rajesh Gupta
University of California at San Diego
,
Vincent Mooney
Georgia Tech. & Nanyang Tech. U.

Copyright © 2011 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 09 October 2011

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ESWeek '11

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ESWeek '11: Seventh Embedded Systems Week

October 9 - 14, 2011

Taipei, Taiwan

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Overall Acceptance Rate 52 of 230 submissions, 23%

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Cited By

Milutinovic SMezzetti EAbella JCazorla F(2019)Increasing the Reliability of Software Timing Analysis for Cache-Based ProcessorsIEEE Transactions on Computers10.1109/TC.2018.289062668:6(836-851)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1109/TC.2018.2890626
Kloda TSolieri MMancuso RCapodieci NValente PBertogna M(2019)Deterministic Memory Hierarchy and Virtualization for Modern Multi-Core Embedded Systems2019 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)10.1109/RTAS.2019.00009(1-14)Online publication date: Apr-2019
https://doi.org/10.1109/RTAS.2019.00009
Su XWu HXue J(2017)An Efficient WCET-Aware Instruction Scheduling and Register Allocation Approach for Clustered VLIW ProcessorsACM Transactions on Embedded Computing Systems10.1145/312652416:5s(1-21)Online publication date: 27-Sep-2017
https://dl.acm.org/doi/10.1145/3126524
Kim YBroman DShrivastava A(2017)WCET-Aware Function-Level Dynamic Code Management on Scratchpad MemoryACM Transactions on Embedded Computing Systems10.1145/306338316:4(1-26)Online publication date: 11-May-2017
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Chatterjee UChakraborty RMukhopadhyay D(2017)A PUF-Based Secure Communication Protocol for IoTACM Transactions on Embedded Computing Systems10.1145/300571516:3(1-25)Online publication date: 28-Apr-2017
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Liu ALiu XWei TYang LRho SPaul A(2017)Distributed Multi-Representative Re-Fusion Approach for Heterogeneous Sensing Data CollectionACM Transactions on Embedded Computing Systems10.1145/297402116:3(1-25)Online publication date: 26-May-2017
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Fleming THuang HBurns AGill CBaruah SLu C(2017)Corrections to and Discussion of “Implementation and Evaluation of Mixed-criticality Scheduling Approaches for Sporadic Tasks”ACM Transactions on Embedded Computing Systems10.1145/297402016:3(1-4)Online publication date: 26-May-2017
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