research-article

Lagrangian relaxation for gate implementation selection

Authors:

Weiping ShiAuthors Info & Claims

ISPD '11: Proceedings of the 2011 international symposium on Physical design

Pages 167 - 174

https://doi.org/10.1145/1960397.1960436

Published: 27 March 2011 Publication History

Abstract

In a typical circuit optimization flow, one essential decision is to select the implementation for each gate according to a cell library. An implementation implies specific gate size, threshold voltage, etc. The selection normally needs to handle multiple and often conflicting objectives. An effective approach for multi-objective optimization is Lagrangian relaxation (LR), which has been adopted in continuous gate sizing. When LR is applied to the gate implementation selection, the Lagrangian dual problem is no longer convex like in continuous gate sizing, and conventional sub-gradient method becomes inefficient. In this paper, we propose a projection-based descent method and a new technique of Lagrangian multiplier distribution for solving the Lagrangian dual problem in discrete space. Experimental results demonstrate that our approach leads to significantly better solution quality and faster convergence compared to the sub-gradient method.

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Cited By

Cheng CHoltz CKahng ALin BMallappa U(2023)DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI GraphsACM Transactions on Design Automation of Electronic Systems10.1145/357701928:4(1-31)Online publication date: 17-May-2023
https://dl.acm.org/doi/10.1145/3577019
Mallappa UCheng C(2021)GRA-LPOProceedings of the 26th Asia and South Pacific Design Automation Conference10.1145/3394885.3431574(697-702)Online publication date: 18-Jan-2021
https://dl.acm.org/doi/10.1145/3394885.3431574
Sharma AChinnery DReimann TBhardwaj SChu C(2019)Fast Lagrangian Relaxation Based Multi-Threaded Gate Sizing Using Simple Timing CalibrationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.2915324(1-1)Online publication date: 2019
https://doi.org/10.1109/TCAD.2019.2915324
Show More Cited By

Index Terms

Lagrangian relaxation for gate implementation selection
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Published In

cover image ACM Conferences

ISPD '11: Proceedings of the 2011 international symposium on Physical design

March 2011

192 pages

ISBN:9781450305501

DOI:10.1145/1960397

General Chair:
Yao-Wen Chang
National Taiwan University
,
Program Chair:
Jiang Hu
Texas A&M University

Copyright © 2011 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 27 March 2011

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ISPD'11: International Symposium on Physical Design

March 27 - 30, 2011

CA, Santa Barbara, USA

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Overall Acceptance Rate 62 of 172 submissions, 36%

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Cited By

Cheng CHoltz CKahng ALin BMallappa U(2023)DAGSizer: A Directed Graph Convolutional Network Approach to Discrete Gate Sizing of VLSI GraphsACM Transactions on Design Automation of Electronic Systems10.1145/357701928:4(1-31)Online publication date: 17-May-2023
https://dl.acm.org/doi/10.1145/3577019
Mallappa UCheng C(2021)GRA-LPOProceedings of the 26th Asia and South Pacific Design Automation Conference10.1145/3394885.3431574(697-702)Online publication date: 18-Jan-2021
https://dl.acm.org/doi/10.1145/3394885.3431574
Sharma AChinnery DReimann TBhardwaj SChu C(2019)Fast Lagrangian Relaxation Based Multi-Threaded Gate Sizing Using Simple Timing CalibrationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.2915324(1-1)Online publication date: 2019
https://doi.org/10.1109/TCAD.2019.2915324
Sharma AChinnery DBhardwaj SChu CMarculescu DLiu F(2015)Fast Lagrangian Relaxation Based Gate Sizing using Multi-ThreadingProceedings of the IEEE/ACM International Conference on Computer-Aided Design10.5555/2840819.2840879(426-433)Online publication date: 2-Nov-2015
https://dl.acm.org/doi/10.5555/2840819.2840879
Sharma AChinnery DBhardwaj SChu C(2015)Fast Lagrangian Relaxation based gate sizing using multi-threading2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)10.1109/ICCAD.2015.7372601(426-433)Online publication date: Nov-2015
https://doi.org/10.1109/ICCAD.2015.7372601
Livramento VGuth CGüntzel JJohann M(2014)A Hybrid Technique for Discrete Gate Sizing Based on Lagrangian RelaxationACM Transactions on Design Automation of Electronic Systems10.1145/264795619:4(1-25)Online publication date: 29-Aug-2014
https://dl.acm.org/doi/10.1145/2647956
Livramento VGuth CGüntzel JJohann MMacii E(2013)Fast and efficient lagrangian relaxation-based discrete gate sizingProceedings of the Conference on Design, Automation and Test in Europe10.5555/2485288.2485725(1855-1860)Online publication date: 18-Mar-2013
https://dl.acm.org/doi/10.5555/2485288.2485725
Ozdal MBurns SHu J(2012)Algorithms for Gate Sizing and Device Parameter Selection for High-Performance DesignsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2012.219627931:10(1558-1571)Online publication date: 1-Oct-2012
https://dl.acm.org/doi/10.1109/TCAD.2012.2196279
dos S. Livramento VGuth CGuntzel JJohann M(2012)Evaluating the impact of slew on delay and power of neighboring gates in discrete gate sizing2012 IEEE 3rd Latin American Symposium on Circuits and Systems (LASCAS)10.1109/LASCAS.2012.6180359(1-4)Online publication date: Feb-2012
https://doi.org/10.1109/LASCAS.2012.6180359
dos S. Livramento VGuth CGuntzel JJohann M(2012)Lagrangian relaxation-based Discrete Gate Sizing for leakage power minimization2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)10.1109/ICECS.2012.6463706(468-471)Online publication date: Dec-2012
https://doi.org/10.1109/ICECS.2012.6463706

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