research-article

Dynamically replicated memory: building reliable systems from nanoscale resistive memories

Authors:

Edmund B. Nightingale,

Thomas MoscibrodaAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 38, Issue 1

Pages 3 - 14

https://doi.org/10.1145/1735970.1736023

Published: 13 March 2010 Publication History

Abstract

DRAM is facing severe scalability challenges in sub-45nm tech- nology nodes due to precise charge placement and sensing hur- dles in deep-submicron geometries. Resistive memories, such as phase-change memory (PCM), already scale well beyond DRAM and are a promising DRAM replacement. Unfortunately, PCM is write-limited, and current approaches to managing writes must de- commission pages of PCM when the first bit fails.

This paper presents dynamically replicated memory (DRM), the first hardware and operating system interface designed for PCM that allows continued operation through graceful degradation when hard faults occur. DRM reuses memory pages that con- tain hard faults by dynamically forming pairs of complementary pages that act as a single page of storage. No changes are required to the processor cores, the cache hierarchy, or the operating sys- tem's page tables. By changing the memory controller, the TLBs, and the operating system to be DRM-aware, we can improve the lifetime of PCM by up to 40x over conventional error-detection techniques.

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Cited By

Sarkar SSikdar BSaha M(2022)Cellular automata based multi-bit stuck-at fault diagnosis for resistive memory基于元胞自动机的电阻存储器多比特固定型故障诊断Frontiers of Information Technology & Electronic Engineering10.1631/FITEE.210025523:7(1110-1126)Online publication date: 25-Jul-2022
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Li TJing NMao ZChen Y(2022)A Hybrid-Grained Remapping Defense Scheme Against Hard Failures for Row-Column-NVMIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.309728841:6(1842-1854)Online publication date: Jun-2022
https://doi.org/10.1109/TCAD.2021.3097288
Zhang YYu ZGu LWang CFeng D(2021)EnTiered-ReRAM: An Enhanced Low Latency and Energy Efficient TLC Crossbar ReRAM ArchitectureIEEE Access10.1109/ACCESS.2021.31298789(167173-167189)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3129878
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Index Terms

Dynamically replicated memory: building reliable systems from nanoscale resistive memories
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory

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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 38, Issue 1

ASPLOS '10

March 2010

399 pages

ISSN:0163-5964

DOI:10.1145/1735970

Issue’s Table of Contents

ASPLOS XV: Proceedings of the fifteenth International Conference on Architectural support for programming languages and operating systems
March 2010
422 pages
ISBN:9781605588391
DOI:10.1145/1736020
General Chair:
James C. Hoe
Carnegie Mellon University, USA
,
Program Chair:
Vikram S. Adve
University of Illinois at Urbana-Champaign, USA

Copyright © 2010 ACM.

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Published: 13 March 2010

Published in SIGARCH Volume 38, Issue 1

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Cited By

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https://doi.org/10.1631/FITEE.2100255
Li TJing NMao ZChen Y(2022)A Hybrid-Grained Remapping Defense Scheme Against Hard Failures for Row-Column-NVMIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.309728841:6(1842-1854)Online publication date: Jun-2022
https://doi.org/10.1109/TCAD.2021.3097288
Zhang YYu ZGu LWang CFeng D(2021)EnTiered-ReRAM: An Enhanced Low Latency and Energy Efficient TLC Crossbar ReRAM ArchitectureIEEE Access10.1109/ACCESS.2021.31298789(167173-167189)Online publication date: 2021
https://doi.org/10.1109/ACCESS.2021.3129878
Liu HChen DJin HLiao XHe BHu KZhang Y(2021)A Survey of Non-Volatile Main Memory Technologies: State-of-the-Arts, Practices, and Future DirectionsJournal of Computer Science and Technology10.1007/s11390-020-0780-z36:1(4-32)Online publication date: 1-Jan-2021
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