Article

Free access

Sequential circuit delay optimization using global path delays

Authors:

Srimat T. Chakradhar,

Sujit Dey,

Miodrag Potkonjak,

Steven G. RothweilerAuthors Info & Claims

DAC '93: Proceedings of the 30th international Design Automation Conference

Pages 483 - 489

https://doi.org/10.1145/157485.164991

Published: 01 July 1993 Publication History

PDF eReader

References

[1]

C. E. Leiserson and J. B. Saxe, "Retiming Synchronous Circuitry," AIgorithmica, vol. 6, pp. 5-35, 1991.

Digital Library

Google Scholar

[2]

G. D. Micheli, "Synchronous Logic Synthesis: Algorithms for Cycle-Time Minimization," IEEE Transactions on Computer-Aided Design, vol. 10, pp. 63-73, January 1991.

Digital Library

Google Scholar

[3]

S. Malik, E. Sentovich, R. Brayton, and A. Sangiovarmi- Vincentelli, "Retiming and Resynthesis: Optimizing Sequential Networks with Combinational Techniques," IEEE Transactzons on Computer-Aided Design, vol. 10, pp. 74- 84, January 1991.

Digital Library

Google Scholar

[4]

S. Dey, M. Potkonjak, and S. Rothweiler, "Performance Optimization of Sequential Circuits by Eliminating Retiming Bottlenecks," in IEEE Proceedings of the International Conference on Computer-Aided Design, November 1992.

Digital Library

Google Scholar

[5]

S.T. Chakradhar, S. Dey, M. Potkonjak, and S. Rothweiler, "Sequential Circuit Delay Optimization Using Global Path Delays," Tech. Rep. 93-C006-4-5506-3, NEC USA, Princeton, N J, 1993.

Digital Library

Google Scholar

[6]

C. H. Papadimitriou and K. Steiglitz, Combinatorial Optimization Algorithms and Complexity. Englewood Cliffs, New Jersey: Prentice Hall, 1982.

Digital Library

Google Scholar

[7]

E. M. Sentovich, K. J. Singh, C. Moon, H. Savoj, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Sequential Circuit Design Using Synthesis and Optimization," in IEEE International Con}erence on Computer Design, pp. 328- 333, October 1992.

Digital Library

Google Scholar

[8]

CPLEX. CPLEX Optimization, Inc., 930 Tahoe Blvd., Bldg. 802, Incline Village, NV 89451-9436, 1992.

Google Scholar

Cited By

View all

El-Maleh AMarchok TRajski JMaly W(2006)Behavior and testability preservation under the retiming transformationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.63121716:5(528-543)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.631217
Chatha KVemuri R(2002)Hardware-Software partitioning and pipelined scheduling of transformative applicationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2002.104332310:3(193-208)Online publication date: 1-Jun-2002
https://dl.acm.org/doi/10.1109/TVLSI.2002.1043323
Bommu SO'Neill NCiesielski M(2000)Retiming-based factorization for sequential logic optimizationACM Transactions on Design Automation of Electronic Systems10.1145/348019.3480685:3(373-398)Online publication date: Jul-2000
https://doi.org/10.1145/348019.348068
Show More Cited By

Index Terms

Sequential circuit delay optimization using global path delays

Recommendations

Extended sequential logic for synchronous circuit optimization and its applications

In this paper, we present a new approach for the extension of sequential logic functionality of D flip-flop in order to perform an additional Boolean function simultaneously along with its usual bit-storage function. We show that a combinational ...
Improving path delay testability of sequential circuits
Special issue on system-level interconnect prediction

We analyze the causes of low path delay fault coverage in synchronous sequential circuits and propose a method to improve testability. The three main reasons for low path delay fault coverage are found to be: (A) combinationally false (nonactivatable) ...
On Redundant Path Delay Faults in Synchronous Sequential Circuits

A path delay fault in a sequential circuit will affect circuit timing only if it can be activated during normal operation of the circuit. Since vector pairs that can be applied to the next-state logic of a nonscan sequential circuit are restricted by ...

Comments

Information & Contributors

Information

Published In

DAC '93: Proceedings of the 30th international Design Automation Conference

July 1993

768 pages

ISBN:0897915771

DOI:10.1145/157485

Chairman:
Alfred E. Dunlop
AT&T Bell Labs., Murray Hill, NJ

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 July 1993

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

DAC93

Sponsor:

EDAC
SIGDA
IEEE-CAS

DAC93: The 30th ACM/IEEE Design Automation Conference

June 14 - 18, 1993

Texas, Dallas, USA

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

Upcoming Conference

DAC '25

Sponsor:
sigda

62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

16
Total Citations
View Citations
377
Total Downloads

Downloads (Last 12 months)64
Downloads (Last 6 weeks)3

Reflects downloads up to 28 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

El-Maleh AMarchok TRajski JMaly W(2006)Behavior and testability preservation under the retiming transformationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/43.63121716:5(528-543)Online publication date: 1-Nov-2006
https://dl.acm.org/doi/10.1109/43.631217
Chatha KVemuri R(2002)Hardware-Software partitioning and pipelined scheduling of transformative applicationsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2002.104332310:3(193-208)Online publication date: 1-Jun-2002
https://dl.acm.org/doi/10.1109/TVLSI.2002.1043323
Bommu SO'Neill NCiesielski M(2000)Retiming-based factorization for sequential logic optimizationACM Transactions on Design Automation of Electronic Systems10.1145/348019.3480685:3(373-398)Online publication date: Jul-2000
https://doi.org/10.1145/348019.348068
Pan P(1999)Performance-driven integration of retiming and resynthesisProceedings of the 36th annual ACM/IEEE Design Automation Conference10.1145/309847.309921(243-246)Online publication date: 1-Jun-1999
https://dl.acm.org/doi/10.1145/309847.309921
Peichen Pan (1999)Performance-driven integration of retiming and resynthesisProceedings 1999 Design Automation Conference (Cat. No. 99CH36361)10.1109/DAC.1999.781319(243-246)Online publication date: 1999
https://doi.org/10.1109/DAC.1999.781319
Iyer BCiesielski MYasuura H(1998)Reencoding for cycle-time minimization under fixed encoding lengthProceedings of the 1998 IEEE/ACM international conference on Computer-aided design10.1145/288548.288631(312-315)Online publication date: 1-Nov-1998
https://dl.acm.org/doi/10.1145/288548.288631
Cong JWu CYoffa EDe Micheli GRabaey J(1997)FPGA synthesis with retiming and pipelining for clock period minimization of sequential circuitsProceedings of the 34th annual Design Automation Conference10.1145/266021.266309(644-649)Online publication date: 13-Jun-1997
https://dl.acm.org/doi/10.1145/266021.266309
Peichen Pan (1997)Continuous retiming: algorithms and applicationsProceedings International Conference on Computer Design VLSI in Computers and Processors10.1109/ICCD.1997.628857(116-121)Online publication date: 1997
https://doi.org/10.1109/ICCD.1997.628857
Cong JChang Wu (1997)Fpga Synthesis With Retiming And Pipelining For Clock Period Minimization Of Sequential CircuitsProceedings of the 34th Design Automation Conference10.1109/DAC.1997.597224(644-649)Online publication date: 1997
https://doi.org/10.1109/DAC.1997.597224
Balakrishnan AChakradhar S(1996)Retiming with logic duplication transformationProceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication10.5555/525699.834783Online publication date: 3-Jan-1996
https://dl.acm.org/doi/10.5555/525699.834783
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Extended sequential logic for synchronous circuit optimization and its applications

Improving path delay testability of sequential circuits

On Redundant Path Delay Faults in Synchronous Sequential Circuits

Comments

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Other Metrics

Article Metrics

Other Metrics

Cited By

PDF

eReader

Login options

Full Access

References

Cited By

Index Terms

Recommendations

Extended sequential logic for synchronous circuit optimization and its applications

Improving path delay testability of sequential circuits

On Redundant Path Delay Faults in Synchronous Sequential Circuits

Comments

Information

Published In

Sponsors

Publisher

Publication History

Permissions

Check for updates

Qualifiers

Conference

Acceptance Rates

Upcoming Conference

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

PDF

eReader

Login options

Full Access

Figures

Other

Share

Share this Publication link

Share on social media

Affiliations