Article

Guaranteeing performance yield in high-level synthesis

Authors:

Yuan XieAuthors Info & Claims

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

Pages 303 - 309

https://doi.org/10.1145/1233501.1233561

Published: 05 November 2006 Publication History

Abstract

Meeting timing constraint is one of the most important issues for modern design automation tools. This situation is exacerbated with the existence of process variation. Current high-level synthesis tools, performing task scheduling, resource allocation and binding, may result in unexpected performance discrepancy due to the ignorance of the impact of process variation, which requires a shift in the design paradigm, from today's deterministic design to statistical or probabilistic design. In this paper, we present a variation-aware performance yield-guaranteed high-level synthesis algorithm. The proposed approach integrates high-level synthesis and statistical static timing analysis into a simulated annealing engine to simultaneously explore solution space while meeting design objectives. Our results show that the area reduction is in the average of 14% when 95% performance yield is imposed with the same total completion time constraint.

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Cited By

Dilek STosun SCakin A(2023)Simulated annealing‐based high‐level synthesis methodology for reliable and energy‐aware application specific integrated circuit designs with multiple supply voltagesInternational Journal of Circuit Theory and Applications10.1002/cta.366651:10(4897-4938)Online publication date: 31-May-2023
https://doi.org/10.1002/cta.3666
Chen YWang YXie YTakach A(2012)Parametric yield-driven resource binding in high-level synthesis with multi-Vth/Vdd library and device sizingJournal of Electrical and Computer Engineering10.1155/2012/1052502012(3-3)Online publication date: 1-Jan-2012
https://dl.acm.org/doi/10.1155/2012/105250
Mittal KJoshi AMutyam M(2011)Timing variation-aware scheduling and resource binding in high-level synthesisACM Transactions on Design Automation of Electronic Systems (TODAES)10.1145/2003695.200370016:4(1-19)Online publication date: 27-Oct-2011
https://dl.acm.org/doi/10.1145/2003695.2003700
Show More Cited By

Index Terms

Guaranteeing performance yield in high-level synthesis
1. Hardware
  1. Electronic design automation
    1. High-level and register-transfer level synthesis
    2. Logic synthesis
      1. Circuit optimization
  2. Hardware validation
2. Mathematics of computing
  1. Probability and statistics
    1. Probabilistic reasoning algorithms
      1. Markov-chain Monte Carlo methods
        Simulated annealing

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Published In

cover image ACM Conferences

ICCAD '06: Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design

November 2006

147 pages

ISBN:1595933891

DOI:10.1145/1233501

General Chair:
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2006 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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SIGDA: ACM Special Interest Group on Design Automation
IEEE-CAS: Circuits & Systems
IEEE-CS: Computer Society

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 November 2006

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ICCAD06: The International Conference on Computer-Aided Design 2006

November 5 - 9, 2006

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Dilek STosun SCakin A(2023)Simulated annealing‐based high‐level synthesis methodology for reliable and energy‐aware application specific integrated circuit designs with multiple supply voltagesInternational Journal of Circuit Theory and Applications10.1002/cta.366651:10(4897-4938)Online publication date: 31-May-2023
https://doi.org/10.1002/cta.3666
Chen YWang YXie YTakach A(2012)Parametric yield-driven resource binding in high-level synthesis with multi-Vth/Vdd library and device sizingJournal of Electrical and Computer Engineering10.1155/2012/1052502012(3-3)Online publication date: 1-Jan-2012
https://dl.acm.org/doi/10.1155/2012/105250
Mittal KJoshi AMutyam M(2011)Timing variation-aware scheduling and resource binding in high-level synthesisACM Transactions on Design Automation of Electronic Systems (TODAES)10.1145/2003695.200370016:4(1-19)Online publication date: 27-Oct-2011
https://dl.acm.org/doi/10.1145/2003695.2003700
Momtazpour MGhorbani MGoudarzi MSanaei EAtienza DXie YAyala JStevens K(2011)Simultaneous variation-aware architecture exploration and task scheduling for MPSoC energy minimizationProceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI10.1145/1973009.1973063(271-276)Online publication date: 2-May-2011
https://dl.acm.org/doi/10.1145/1973009.1973063
Lucas GChen DScheffer LPhillips JHu A(2010)Variation-aware layout-driven scheduling for performance yield optimizationProceedings of the International Conference on Computer-Aided Design10.5555/2133429.2133433(17-24)Online publication date: 7-Nov-2010
https://dl.acm.org/doi/10.5555/2133429.2133433
Chen YXie YWang YTakach ALin Y(2010)Parametric yield driven resource binding in behavioral synthesis with multi-V/V libraryProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899901(781-786)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899901
MOMTAZPOUR MGOUDARZI MSANAEI E(2010)Variation-Aware Task and Communication Scheduling in MPSoCs for Power-Yield MaximizationIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E93.A.2542E93-A:12(2542-2550)Online publication date: 2010
https://doi.org/10.1587/transfun.E93.A.2542
Chon HKim TWakabayashi K(2009)Timing variation-aware task scheduling and binding for MPSoCProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509680(137-142)Online publication date: 19-Jan-2009
https://dl.acm.org/doi/10.5555/1509633.1509680
Wang FXie YTakach AWakabayashi K(2009)Variation-aware resource sharing and binding in behavioral synthesisProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509653(79-84)Online publication date: 19-Jan-2009
https://dl.acm.org/doi/10.5555/1509633.1509653
Chen YXie YWakabayashi K(2009)Tolerating process variations in high-level synthesis using transparent latchesProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509652(73-78)Online publication date: 19-Jan-2009
https://dl.acm.org/doi/10.5555/1509633.1509652
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