Article

Free access

Efficient instruction scheduling for a pipelined architecture

Authors:

Philip B. Gibbons,

Steven S. MuchnickAuthors Info & Claims

SIGPLAN '86: Proceedings of the 1986 SIGPLAN symposium on Compiler construction

Pages 11 - 16

https://doi.org/10.1145/12276.13312

Published: 01 July 1986 Publication History

Abstract

As part of an effort to develop an optimizing compiler for a pipelined architecture, a code reorganization algorithm has been developed that significantly reduces the number of runtime pipeline interlocks. In a pass after code generation, the algorithm uses a dag representation to heuristically schedule the instructions in each basic block.

Previous algorithms for reducing pipeline interlocks have had worst-case runtimes of at least O (n⁴). By using a dag representation which prevents scheduling deadlocks and a selection method that requires no lookahead, the resulting algorithm reorganizes instructions almost as effectively in practice, while having an O (n²) worst-case runtime.

References

[1]

Arya, S. Optimal Instruction Scheduling for a Class of Vector Processors: An Integer Programming Approach. Tech. Rept. CRL-TR-19-83, Computer Research Laboratory, the Univ. of Michigan, Ann Arbor, April 1983.

[2]

Auslander, M. & M. Hopkins. An Overview of the PL.8 Compiler. Proc. ACM SIGPLAN Syrup. on Compiler Construction, Boston, June 1982, pp. 22 - 31.

Digital Library

[3]

Conway, R.W., W.L. Maxwell & L.W. Miller, Theory of Scheduling, Addison-Wesley, Reading, MA, 1967.

[4]

Coutant, D.S. Retargetable High-Level Alias Analysis, Proc. ACM Syrup. on Princ. of Prog. Lang., St. Petersburg Beach, FL, January 1986, pp. 110- 118.

Digital Library

[5]

Davidson, S., D. Landskov, B.D. Shriver & P.W. Mallett. Some Experiments in Local Microcode Compaction for Horizontal Machines. 1EEE Trans. on Computers, Vol. C-30, No. 7, July 1981, pp. 460 - 477.

[6]

Fisher, j.A. Trace Scheduling: A Technique for Global Microcode Compaction. IEEE Trans. on Computers, Vol. C-30, No. 7, July 1981, pp. 478 - 490.

[7]

Gross, T.R. Code Optimization of Pipeline Constraints. Tech. Rept. 83-255, Computer Systems Lab., Stanford Univ., Dec. 1983.

[8]

Hennessy, J.L. Symbolic Debugging of Optimized Code, ACM Trans. on Prog. Lang. and Sys., Vol. 3, No. 1, Jan. 1981, pp. 200 - 206.

[9]

Hennessy, J.L. & T.R. Gross. Postpass Code Optimization of Pipeline Constraints. ACM Trans. on Prog. Lang. and Sys, Vol. 5, No. 3, July 1983, pp. 422- 448.

Digital Library

[10]

johnson, M.S. & T.C. Miller. Effectiveness of a Machine-Level, Global Optimizer, Proc. of the SIGPLAN '86 Conf. on Comp. Constr., June 1986.

Digital Library

[11]

Knuth, D.E. Fundamental Algorithms, Addison- Wesley, Reading, MA, p. 258.

[12]

Kogge, P.M. The Architecture of Pipelined Computers, McGraw-Hill, New York, 1981.

[13]

Rymarczyk, J.W. Coding Guidelines for Pipelined Processors, Proc. of the Symp. on Arch. Supt. for Prog. Lang. and Oper. Syst., Palo Alto, CA, March 1982, pp. 12- 19.

Digital Library

[14]

Sites, R.L. Instruction Ordering for the Cray-1 Computer. Tech. Rept. 78-CS-023, Univ. of California, San Diego, July 1978.

[15]

Spillman, Thomas C., Exposing Side-Effects in a PldI Optimizing Compiler, Information Processing 81, North:Holland, 1972, pp. 376 - 381.

[16]

Thornton, J.E. Parallel Operation in the Control Data 6600, Proc. Fall Joint Comp. Conf., Part 2, Vol. 26, 1964, pp. 33 -40.

[17]

Tokoru, M., E. Tamura & T. Takizuka. Optimization of Microprograms. IEEE Trans. on Computers, Vol. C-30, No. 7, July 1981, pp. 491 - 504.

[18]

Tomasulo, R.M. An Efficient Algorithm for Exploiting Multiple Arithmetic Units, IBM J. of Res. and Devt., Vol. 11, No. 1, Jan. 1967, pp. 25 - 33.

Digital Library

[19]

Vegdahl, S. Local Code Generation and Compaction in Optimizing Microcode Compilers, Ph.D. thesis, Carnegie-Mellon Univ., De~. 1982.

Digital Library

[20]

Zellweger, P.T. lnteractiv~ Source-Level Debugging of Optimized Programs, Research Report CSL-84-5, Xerox Palo Alto Research Center, Palo Alto, CA, May 1984.

Cited By

Yang ZShirako JSarkar V(2024)Fully Verified Instruction SchedulingProceedings of the ACM on Programming Languages10.1145/36897398:OOPSLA2(791-816)Online publication date: 8-Oct-2024
https://dl.acm.org/doi/10.1145/3689739
Wei ZYu JRen JDuan WWu D(2024)Progressive Simulated Annealing Algorithm for the Pipeline Allocation Problem of Protocol Independent Switch Architecture Chips2024 6th International Conference on Data-driven Optimization of Complex Systems (DOCS)10.1109/DOCS63458.2024.10704552(243-249)Online publication date: 16-Aug-2024
https://doi.org/10.1109/DOCS63458.2024.10704552
Krolik AVerbrugge CHendren L(2023)rNdN: Fast Query Compilation for NVIDIA GPUsACM Transactions on Architecture and Code Optimization10.1145/360350320:3(1-25)Online publication date: 19-Jul-2023
https://dl.acm.org/doi/10.1145/3603503
Show More Cited By

Recommendations

Retargetable instruction scheduling for pipelined processors
Code generation and instruction scheduling for pipelined sisd machines
Dynamic instruction scheduling in a trace-based multi-threaded architecture

Simulation results are presented using the hardware-implemented, trace-based dynamic instruction scheduler of our single process DTSVLIW architecture to schedule instructions from several processes into multiple streams of VLIW instructions for ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

SIGPLAN '86: Proceedings of the 1986 SIGPLAN symposium on Compiler construction

July 1986

275 pages

ISBN:0897911970

DOI:10.1145/12276

Editor:
Richard L Wexelblat
Philips Laboratories, Briarcliff Manor, NY

ACM SIGPLAN Notices Volume 21, Issue 7
July 1986
275 pages
ISSN:0362-1340
EISSN:1558-1160
DOI:10.1145/13310
Editor:
Richard L. Wexelblat
Philips Laboratories, Briarcliff Manor, NY
Issue’s Table of Contents

Copyright © 1986 Authors.

Sponsors

SIGPLAN: ACM Special Interest Group on Programming Languages

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 July 1986

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Article

Conference

SCC86

Sponsor:

SIGPLAN

SCC86: SIGPLAN Symposium on Compiler Construction

June 25 - 27, 1986

California, Palo Alto, USA

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

196
Total Citations
View Citations
2,004
Total Downloads

Downloads (Last 12 months)198
Downloads (Last 6 weeks)32

Reflects downloads up to 24 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

Yang ZShirako JSarkar V(2024)Fully Verified Instruction SchedulingProceedings of the ACM on Programming Languages10.1145/36897398:OOPSLA2(791-816)Online publication date: 8-Oct-2024
https://dl.acm.org/doi/10.1145/3689739
Wei ZYu JRen JDuan WWu D(2024)Progressive Simulated Annealing Algorithm for the Pipeline Allocation Problem of Protocol Independent Switch Architecture Chips2024 6th International Conference on Data-driven Optimization of Complex Systems (DOCS)10.1109/DOCS63458.2024.10704552(243-249)Online publication date: 16-Aug-2024
https://doi.org/10.1109/DOCS63458.2024.10704552
Krolik AVerbrugge CHendren L(2023)rNdN: Fast Query Compilation for NVIDIA GPUsACM Transactions on Architecture and Code Optimization10.1145/360350320:3(1-25)Online publication date: 19-Jul-2023
https://dl.acm.org/doi/10.1145/3603503
Leopoldseder DSchatz RStadler LRigger MWürthinger TMössenböck HTilevich EMössenböck H(2018)Fast-path loop unrolling of non-counted loops to enable subsequent compiler optimizationsProceedings of the 15th International Conference on Managed Languages & Runtimes10.1145/3237009.3237013(1-13)Online publication date: 12-Sep-2018
https://dl.acm.org/doi/10.1145/3237009.3237013
Aiken ABanerjee UKejariwal ANicolau AAiken ABanerjee UKejariwal ANicolau A(2016)Overview of ILP ArchitecturesInstruction Level Parallelism10.1007/978-1-4899-7797-7_2(9-42)Online publication date: 30-Nov-2016
https://doi.org/10.1007/978-1-4899-7797-7_2
Goodman JHsu W(2014)Code scheduling and register allocation in large basic blocksACM International Conference on Supercomputing 25th Anniversary Volume10.1145/2591635.2667158(88-98)Online publication date: 10-Jun-2014
https://dl.acm.org/doi/10.1145/2591635.2667158
Jantz MKulkarni P(2014)Analyzing and addressing false interactions during compiler optimization phase orderingSoftware—Practice & Experience10.1002/spe.217644:6(643-679)Online publication date: 1-Jun-2014
https://dl.acm.org/doi/10.1002/spe.2176
Aslam MRea SPesch D(2013)Provisioning within a WSAN cloud conceptACM SIGBED Review10.1145/2492385.249239410:1(48-53)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1145/2492385.2492394
Hatvani LSeceleanu CPettersson P(2013)Modeling and analysis of adaptive embedded systems using adaptive task automataACM SIGBED Review10.1145/2492385.249239310:1(43-47)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1145/2492385.2492393
Heinrich PPrehofer C(2013)Network-wide energy optimization for adaptive embedded systemsACM SIGBED Review10.1145/2492385.249239110:1(33-36)Online publication date: 1-Feb-2013
https://dl.acm.org/doi/10.1145/2492385.2492391
Show More Cited By

View Options

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

Media

Figures

Other

Tables

View Table of Contents