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NANA: A nano-scale active network architecture

Published: 01 January 2006 Publication History

Abstract

This article explores the architectural challenges introduced by emerging bottom-up fabrication of nanoelectronic circuits. The specific nanotechnology we explore proposes patterned DNA nanostructures as a scaffold for the placement and interconnection of carbon nanotube or silicon nanorod FETs to create a limited size circuit (node). Three characteristics of this technology that significantly impact architecture are (1) limited node size, (2) random node interconnection, and (3) high defect rates. We present and evaluate an accumulator-based active network architecture that is compatible with any technology that presents these three challenges. This architecture represents an initial, unoptimized solution for understanding the implications of DNA-guide self-assembly.

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cover image ACM Journal on Emerging Technologies in Computing Systems
ACM Journal on Emerging Technologies in Computing Systems  Volume 2, Issue 1
January 2006
63 pages
ISSN:1550-4832
EISSN:1550-4840
DOI:10.1145/1126257
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Association for Computing Machinery

New York, NY, United States

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Publication History

Published: 01 January 2006
Published in JETC Volume 2, Issue 1

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Author Tags

  1. Accumulator ISA
  2. DNA
  3. active network
  4. carbon nanotube
  5. defect isolation
  6. defect tolerance
  7. nanocomputing
  8. nanoelectronics
  9. reverse path forwarding
  10. self-assembly

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