Article

A unified processor architecture for RISC & VLIW DSP

Authors:

Chia-Hsien Liu,

Chein-Wei JenAuthors Info & Claims

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

Pages 50 - 55

https://doi.org/10.1145/1057661.1057675

Published: 17 April 2005 Publication History

Abstract

This paper presents a unified processor core with two operation modes. The processor core works as a compiler-friendly MIPS-like core in the RISC mode, and it is a 4-way VLIW in its DSP mode, which has distributed and ping-pong register organization optimized for stream processing. To minimize hardware, the DSP mode has no control construct for program flow, while the data manipulation RISC instructions are executed in the DSP datapath. Moreover, the two operation modes can be changed instruction by instruction within a single program stream via the hierarchical instruction encoding, which also helps to reduce the VLIW code sizes significantly. The processor has been implemented in the UMC 0.18um CMOS technology, and its core size is 3.23mmx3.23mm including the 32KB on-chip memory. It can operate at 208MHz while consuming 380.6mW average power.

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Hepola KMultanen JJääskeläinen P(2022)Dual-IS: Instruction Set Modality for Efficient Instruction Level ParallelismArchitecture of Computing Systems10.1007/978-3-031-21867-5_2(17-32)Online publication date: 13-Sep-2022
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Index Terms

A unified processor architecture for RISC & VLIW DSP
1. Computer systems organization
  1. Architectures

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Published In

cover image ACM Conferences

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

April 2005

518 pages

ISBN:1595930574

DOI:10.1145/1057661

General Chair:
John Lach
University of Virginia
,
Program Chairs:
Gang Qu
University of Maryland, College Park
,
Yehea Ismail
Northwestern University

Copyright © 2005 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 17 April 2005

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GLSVLSI05

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GLSVLSI05: Great Lakes Symposium on VLSI 2005

April 17 - 19, 2005

Illinois, Chicago, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Hepola KMultanen JJääskeläinen P(2024)Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set ModeIEEE Transactions on Computers10.1109/TC.2023.333731373:2(560-573)Online publication date: 1-Feb-2024
https://dl.acm.org/doi/10.1109/TC.2023.3337313
Hepola KMultanen JJääskeläinen P(2022)Dual-IS: Instruction Set Modality for Efficient Instruction Level ParallelismArchitecture of Computing Systems10.1007/978-3-031-21867-5_2(17-32)Online publication date: 13-Sep-2022
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Hou YHe HYang XGuo DWang XFu JQiu K(2016)FuMicroVLSI Design10.1155/2016/87879192016(2)Online publication date: 1-Dec-2016
https://dl.acm.org/doi/10.1155/2016/8787919
Wu CLu CLee J(2014)Register spilling via transformed interference equations for PAC DSP architectureConcurrency and Computation: Practice & Experience10.1002/cpe.305126:3(779-799)Online publication date: 10-Mar-2014
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Chang DLin TWu CLee JChu YWu A(2011)Parallel Architecture Core (PAC)--the First Multicore Application Processor SoC in Taiwan Part IJournal of Signal Processing Systems10.1007/s11265-010-0470-062:3(373-382)Online publication date: 1-Mar-2011
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Chiu JYang K(2010)A Novel instruction stream buffer for VLIW architecturesComputers and Electrical Engineering10.1016/j.compeleceng.2009.08.00636:1(190-198)Online publication date: 1-Jan-2010
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Lin TChen SKuo YLiu CHsiao P(2008)Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia ApplicationsJournal of Signal Processing Systems10.1007/s11265-007-0061-x51:3(209-223)Online publication date: 1-Jun-2008
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Lin YLu CWu CTang CYou YMoo YLee J(2008)Effective Code Generation for Distributed and Ping-Pong Register FilesJournal of Signal Processing Systems10.1007/s11265-007-0059-451:3(269-288)Online publication date: 1-Jun-2008
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Hsiao PLin TLiu CJen C(2007)Latency-Tolerant Virtual Cluster Architecture for VLIW DSP2007 IEEE International Symposium on Circuits and Systems10.1109/ISCAS.2007.378438(3506-3509)Online publication date: May-2007
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Wu CChen SLee J(2006)Copy propagation optimizations for VLIW DSP processors with distributed register filesProceedings of the 19th international conference on Languages and compilers for parallel computing10.5555/1757112.1757139(251-266)Online publication date: 2-Nov-2006
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