A General Failure Candidate Ranking Framework for Silicon Debug
Abstract
Index Terms
- A General Failure Candidate Ranking Framework for Silicon Debug
Recommendations
Silicon debug of a co-processor array for video applications
HLDVT '00: Proceedings of the IEEE International High-Level Validation and Test Workshop (HLDVT'00)For today's multi-million transistor ICs, existing design verification techniques cannot guarantee that first silicon is designed error free. Because of this reality, there is a need for a good debug methodology. This paper describes the application of ...
On-chip delay measurement for silicon debug
GLSVLSI '04: Proceedings of the 14th ACM Great Lakes symposium on VLSIEfficient test and debug techniques are indispensable for performance characterization of large complex integrated circuits in deep-submicron and nanometer technologies. Performance characterization of such chips requires on-chip hardware and efficient ...
Buried silicon-Germanium pMOSFETs: experimental analysis in VLSI logic circuits under aggressive voltage scaling
In this paper, the potential of Silicon-Germanium (SiGe) technology for VLSI logic applications is investigated from a circuit perspective for the first time. The study is based on experimental measurements on 45-nm SiGe pMOSFETs with a high-κ/metal ...
Comments
Information & Contributors
Information
Published In
Publisher
IEEE Computer Society
United States
Publication History
Author Tag
Qualifiers
- Article
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 0Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0