skip to main content
research-article

Design of Accurate Low-Cost On-Chip Structures for Protecting Integrated Circuits Against Recycling

Published: 01 April 2016 Publication History

Abstract

The recycling of electronic components has become a major industrial and governmental concern, as it could potentially impact the security and reliability of a wide variety of electronic systems. It is extremely challenging to detect a recycled integrated circuit (IC) that is already used for a very short period of time because the process variations outpace the degradation caused by aging, especially in lower technology nodes. In this paper, we propose a suite of solutions, based on lightweight negative bias temperature instability (NBTI)-aware ring oscillators (ROs), for combating die and IC recycling (CDIR) when ICs are used for a very short duration. The proposed solutions are implemented in the 90-nm technology node. The simulation results demonstrate that our newly proposed NBTI-aware multiple pair RO-based CDIRs can detect ICs used only for a few hours.

References

[1]
U. Guin, X. Zhang, D. Forte, and M. Tehranipoor, “Low-cost on-chip structures for combating die and IC recycling,” in Proc. 51st ACM/EDAC/IEEE Design Autom. Conf., Jun. 2014, pp. 1–6.
[2]
U. Guin, D. DiMase, and M. Tehranipoor, “Counterfeit integrated circuits: Detection, avoidance, and the challenges ahead,” J. Electron. Test., vol. 30, no. 1, pp. 9–23, 2014.
[3]
U. Guin, D. Forte, and M. Tehranipoor, “Anti-counterfeit techniques: From design to resign,” in Proc. 14th Int. Workshop Microprocessor Test Verification (MTV), Dec. 2013, pp. 89–94.
[4]
U. Guin, K. Huang, D. DiMase, J. M. Carulli, M. Tehranipoor, and Y. Makris, “Counterfeit integrated circuits: A rising threat in the global semiconductor supply chain,” Proc. IEEE, vol. 102, no. 8, pp. 1207–1228, Aug. 2014.
[5]
L. W. Kessler and T. Sharpe, “Faked parts detection,” Circuits Assembly, J. Surf. Mount Electron. Assembly, Jun. 2010.
[6]
J. Cassell, Reports of Counterfeit Parts Quadruple Since 2009, Challenging US Defense Industry and National Security, Apr. 2012.
[7]
Top 5 Most Counterfeited Parts Represent a $169 Billion Potential Challenge for Global Semiconductor Market, IHS, 2011.
[8]
M. Tehranipoor, U. Guin, and D. Forte, Counterfeit Integrated Circuits: Detection and Avoidance. New York, NY, USA: Springer-Verlag, 2015.
[9]
B. Hughitt, “Counterfeit electronic parts,” in Proc. NEPP Electron. Technol. Workshop, Jun. 2010.
[10]
F. Koushanfar et al., “Can EDA combat the rise of electronic counterfeiting?” in Proc. 49th ACM/EDAC/IEEE Design Autom. Conf. (DAC), Jun. 2012, pp. 133–138.
[11]
SAE. Test Methods Standard; Counterfeit Electronic Parts. [Online]. Available: http://standards.sae.org/wip/as6171/.
[12]
U. Guin, D. DiMase, and M. Tehranipoor, “A comprehensive framework for counterfeit defect coverage analysis and detection assessment,” J. Electron. Test., vol. 30, no. 1, pp. 25–40, 2014.
[13]
X. Zhang, K. Xiao, and M. Tehranipoor, “Path-delay fingerprinting for identification of recovered ICs,” in Proc. IEEE Int. Symp. Fault Defect Tolerance VLSI Syst., Oct. 2012, pp. 13–18.
[14]
K. Huang, J. M. Carulli, and Y. Makris, “Parametric counterfeit IC detection via support vector machines,” in Proc. IEEE Int. Symp. Fault Defect Tolerance VLSI Syst., Oct. 2012, pp. 7–12.
[15]
Y. Zheng, X. Wang, and S. Bhunia, “SACCI: Scan-based characterization through clock phase sweep for counterfeit chip detection,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 23, no. 5, pp. 831–841, May 2014.
[16]
Y. Zheng, A. Basak, and S. Bhunia, “CACI: Dynamic current analysis towards robust recycled chip identification,” in Proc. 51st ACM/EDAC/IEEE Design Autom. Conf. (DAC), Jun. 2014, pp. 1–6.
[17]
H. Dogan, D. Forte, and M. M. Tehranipoor, “Aging analysis for recycled FPGA detection,” in Proc. IEEE Int. Symp. Defect Fault Tolerance VLSI Nanotechnol. Syst. (DFT), Oct. 2014, pp. 171–176.
[18]
E. Karl, P. Singh, D. Blaauw, and D. Sylvester, “Compact in-situ sensors for monitoring negative-bias-temperature-instability effect and oxide degradation,” in IEEE Int. Solid-State Circuits Conf. (ISSCC), Dig. Tech. Papers, Feb. 2008, pp. 410–623.
[19]
T.-H. Kim, R. Persaud, and C. H. Kim, “Silicon odometer: An on-chip reliability monitor for measuring frequency degradation of digital circuits,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 874–880, Apr. 2008.
[20]
J. Keane, X. Wang, D. Persaud, and C. H. Kim, “An all-in-one silicon odometer for separately monitoring HCI, BTI, and TDDB,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 817–829, Apr. 2010.
[21]
J. Keane, W. Zhang, and C. H. Kim, “An array-based odometer system for statistically significant circuit aging characterization,” IEEE J. Solid-State Circuits, vol. 46, no. 10, pp. 2374–2385, Oct. 2011.
[22]
K. Hofmann et al., “Highly accurate product-level aging monitoring in 40 nm CMOS,” in Proc. Symp. VLSI Technol. (VLSIT), Jun. 2010, pp. 27–28.
[23]
E. Saneyoshi, K. Nose, and M. Mizuno, “A precise-tracking NBTI-degradation monitor independent of NBTI recovery effect,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers (ISSCC), Feb. 2010, pp. 192–193.
[24]
X. Zhang, N. Tuzzio, and M. Tehranipoor, “Identification of recovered ICs using fingerprints from a light-weight on-chip sensor,” in Proc. 49th ACM/EDAC/IEEE Design Autom. Conf., Jun. 2012, pp. 703–708.
[25]
X. Zhang and M. Tehranipoor, “Design of on-chip lightweight sensors for effective detection of recycled ICs,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 5, pp. 1016–1029, May 2014.
[26]
M. A. Alam and S. Mahapatra, “A comprehensive model of PMOS NBTI degradation,” Microelectron. Rel., vol. 45, no. 1, pp. 71–81, 2005.
[27]
S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, and S. Vrudhula, “Predictive modeling of the NBTI effect for reliable design,” in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2006, pp. 189–192.
[28]
V. Reddy et al., “Impact of negative bias temperature instability on digital circuit reliability,” in Proc. 40th Annu. Rel. Phys. Symp., 2002, pp. 248–254.
[29]
K.-L. Chen, S. A. Saller, I. A. Groves, and D. B. Scott, “Reliability effects on MOS transistors due to hot-carrier injection,” IEEE Trans. Electron Devices, vol. 32, no. 2, pp. 386–393, Feb. 1985.
[30]
S. Mahapatra, D. Saha, D. Varghese, and P. B. Kumar, “On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress,” IEEE Trans. Electron Devices, vol. 53, no. 7, pp. 1583–1592, Jul. 2006.
[31]
J. W. McPherson, “Reliability challenges for 45 nm and beyond,” in Proc. 43rd ACM/IEEE Design Autom. Conf., Jul. 2006, pp. 176–181.
[32]
J. Chen, S. Wang, and M. Tehranipoor, “Efficient selection and analysis of critical-reliability paths and gates,” in Proc. GLSVLSI, 2012, pp. 45–50.
[33]
M. K. Steven, Fundamentals of Statistical Signal Processing. Englewood Cliffs, NJ, USA: Prentice-Hall, 1993.
[34]
Predictive Technology Model (PTM). [Online]. Available: http://ptm.asu.edu/.
[35]
T. Sato, T. Kozaki, T. Uezono, H. Tsutsui, and H. Ochi, “A device array for efficient bias-temperature instability measurements,” in Proc. Eur. Solid-State Device Res. Conf. (ESSDERC), Sep. 2011, pp. 143–146.
[37]
C. Helfmeier, D. Nedospasov, C. Tarnovsky, J. S. Krissler, C. Boit, and J.-P. Seifert, “Breaking and entering through the silicon,” in Proc. ACM SIGSAC Conf. Comput. Commun. Secur., 2013, pp. 733–744.
[38]
M. Agarwal, B. C. Paul, M. Zhang, and S. Mitra, “Circuit failure prediction and its application to transistor aging,” in Proc. 25th IEEE VLSI Test Symp., May 2007, pp. 277–286.

Cited By

View all

Index Terms

  1. Design of Accurate Low-Cost On-Chip Structures for Protecting Integrated Circuits Against Recycling
              Index terms have been assigned to the content through auto-classification.

              Recommendations

              Comments

              Information & Contributors

              Information

              Published In

              cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems
              IEEE Transactions on Very Large Scale Integration (VLSI) Systems  Volume 24, Issue 4
              April 2016
              400 pages

              Publisher

              IEEE Educational Activities Department

              United States

              Publication History

              Published: 01 April 2016

              Qualifiers

              • Research-article

              Contributors

              Other Metrics

              Bibliometrics & Citations

              Bibliometrics

              Article Metrics

              • Downloads (Last 12 months)0
              • Downloads (Last 6 weeks)0
              Reflects downloads up to 06 Jan 2025

              Other Metrics

              Citations

              Cited By

              View all

              View Options

              View options

              Media

              Figures

              Other

              Tables

              Share

              Share

              Share this Publication link

              Share on social media