research-article

High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm

Authors:

Thomas M. ConteAuthors Info & Claims

IEEE Transactions on Parallel and Distributed Systems, Volume 16, Issue 12

Pages 1132 - 1142

https://doi.org/10.1109/TPDS.2005.150

Published: 01 December 2005 Publication History

Abstract

This paper presents a cost-effective and high-performance dual-thread VLIW processor model. The dual-thread VLIW processor model is a low-cost subset of the Weld architecture paradigm. It supports one main thread and one speculative thread running simultaneously in a VLIW processor with a register file and a fetch unit per thread along with memory disambiguation hardware for speculative load and store operations. This paper analyzes the performance impact of the dual-thread VLIW processor, which includes analysis of migrating disambiguation hardware for speculative load operations to the compiler and of the sensitivity of the model to the variation of branch misprediction, second-level cache miss penalties, and register file copy time. Up to 34 percent improvement in performance can be attained using the dual-thread VLIW processor when compared to a single-threaded VLIW processor model.

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Cited By

Tran KJimborean ACarlson TKoukos KSjälander MKaxiras S(2018)SWOOP: software-hardware co-design for non-speculative, execute-ahead, in-order coresACM SIGPLAN Notices10.1145/3296979.319239353:4(328-343)Online publication date: 11-Jun-2018
https://dl.acm.org/doi/10.1145/3296979.3192393
Tran KJimborean ACarlson TKoukos KSjälander MKaxiras SFoster JGrossman D(2018)SWOOP: software-hardware co-design for non-speculative, execute-ahead, in-order coresProceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/3192366.3192393(328-343)Online publication date: 11-Jun-2018
https://dl.acm.org/doi/10.1145/3192366.3192393
Rounce PDe Souza A(2008)Dynamic instruction scheduling in a trace-based multi-threaded architectureInternational Journal of Parallel Programming10.1007/s10766-007-0062-136:2(184-205)Online publication date: 1-Apr-2008
https://dl.acm.org/doi/10.1007/s10766-007-0062-1
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High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm

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cover image IEEE Transactions on Parallel and Distributed Systems

IEEE Transactions on Parallel and Distributed Systems Volume 16, Issue 12

December 2005

96 pages

ISSN:1045-9219

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Copyright © 2005.

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IEEE Press

Publication History

Published: 01 December 2005

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Cited By

Tran KJimborean ACarlson TKoukos KSjälander MKaxiras S(2018)SWOOP: software-hardware co-design for non-speculative, execute-ahead, in-order coresACM SIGPLAN Notices10.1145/3296979.319239353:4(328-343)Online publication date: 11-Jun-2018
https://dl.acm.org/doi/10.1145/3296979.3192393
Tran KJimborean ACarlson TKoukos KSjälander MKaxiras SFoster JGrossman D(2018)SWOOP: software-hardware co-design for non-speculative, execute-ahead, in-order coresProceedings of the 39th ACM SIGPLAN Conference on Programming Language Design and Implementation10.1145/3192366.3192393(328-343)Online publication date: 11-Jun-2018
https://dl.acm.org/doi/10.1145/3192366.3192393
Rounce PDe Souza A(2008)Dynamic instruction scheduling in a trace-based multi-threaded architectureInternational Journal of Parallel Programming10.1007/s10766-007-0062-136:2(184-205)Online publication date: 1-Apr-2008
https://dl.acm.org/doi/10.1007/s10766-007-0062-1
Wu KKanstein AMadsen JBerekovic M(2007)Mt-ADRESProceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications10.5555/1764631.1764635(26-38)Online publication date: 27-Mar-2007
https://dl.acm.org/doi/10.5555/1764631.1764635

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