LIAD: A Method for Extending the Effective Time of 3-D TLC NAND Flash Hard Decision
Authors: 
Xiaolei Yu, Jing He, Qianhui Li, Bo Zhang, Xianliang Wang, Liu Yang, Tianchun Ye, Qi Wang, Zongliang HuoAuthors Info & Claims
Xiaolei Yu, Jing He, Qianhui Li, Bo Zhang, Xianliang Wang, Liu Yang, Tianchun Ye, Qi Wang, Zongliang HuoAuthors Info & ClaimsPages 1705 - 1717
Abstract
Triple-level cell NAND flash memory is widely used today due to its higher storage density and capacity. However, with the increase in the storage density, lower reliability results in more read times for flash memory and significantly reduces the read performance. In order to avoid unnecessary read operations, this article proposes a hard decision–soft decoding method called location information-assisted decoding (LIAD) method, which determines the additional information required for decoding by mutual information, and then transmits the required information to correct the log-likelihood ratio (LLR). Different from the conventional LLR correction algorithm, this method does not require additional read operations and correct data. Only using sensing results, our method can reduce uncorrectable error bit rate (UBER) by up to 99%, and the system read latency under SSDsim (Hu et al. 2011) simulation can be reduced by up to 53%.
References
[1]
Y. Hu, H. Jiang, D. Feng, L. Tian, and S. P. Zhang, “Performance impact and interplay of SSD parallelism through advanced commands, allocation strategy and data granularity,” in Proc. Int. Conf. Supercomput., 2011, pp. 96–107.
[2]
J. Wang, T. A. Courtade, H. Shankar, and R. D. Wesel, “Soft information for LDPC decoding in flash: Mutual-information optimized quantization,” in Proc. Global Telecommun. Conf., 2011, pp. 1–6.
[3]
C. A. Aslam, Y. L. Guan, and K. Cai, “Read and write voltage signal optimization for multi-level-cell (MLC) nand flash memory,” IEEE Trans. Commun., vol. 64, no. 4, pp. 1613–1623, Apr. 2016.
[4]
F. Wuet al., “Using error modes aware LDPC to improve decoding performance of 3D TLC nand flash,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 39, no. 4, pp. 909–921, Apr. 2020.
[5]
J. Wang, G. Dong, Z. Tong, and R. D. Wesel, “Mutual-information optimized quantization for LDPC decoding of accurately modeled flash data,” 2012, arxiv.abs/1202.1325.
[6]
F. Chen, D. A. Koufaty, and X. Zhang, “Understanding intrinsic characteristics and system implications of flash memory based solid state drives,” Perform. Eval. Rev., vol. 37, no. 1, pp. 181–192, 2009.
[7]
X. Y. Hu, E. Eleftheriou, and D. M. Arnold, “Progressive edge-growth tanner graphs,” in Proc. IEEE Global Telecommun. Conf., 2002, pp. 1–8.
[8]
T. Richardson, “Error-floors of LDPC codes,” in Proc. Allerton Conf. Commun. Control Comput., Monticello, IL, USA, Oct. 2003.
[9]
J. Wang, L. Dolecek, and R. Wesel, “Controlling LDPC absorbing sets via the null space of the cycle consistency matrix,” in Proc. ICC, 2011, pp. 1–6.
[10]
J. Wang, L. Dolecek, and R. Wesel, “LDPC absorbing sets, the null space of the cycle consistency matrix, and Tanner’s constructions,” in Proc. Inf. Theory Appl. Workshop, 2011, pp. 455–459.
[11]
M. Ivkovic, S. K. Chilappagari, and B. Vasic, “Eliminating trapping sets in low-density parity-check codes by using Tanner graph covers,” IEEE Trans. Inf. Theory, vol. 54, no. 8, pp. 3763–3768, Aug. 2008.
[12]
D. V. Nguyen, B. Vasic, M. Marcellin, and S. K. Chilappagari, “Structured LDPC codes from permutation matrices free of small trapping sets,” in Proc. IEEE Inf. Theory Workshop, 2010, pp. 1–5.
[13]
H. Qin, Q. Diao, L. Shu, and K. Abdel-Ghaffar, “Cyclic and quasi-cyclic LDPC codes: New developments,” in Proc. Inf. Theory Appl. Workshop, 2011, pp. 186–195.
[14]
L. Qiao, S. Liang, C. J. Xue, Q. Zhuge, and H. M. Sha, “Improving LDPC performance via asymmetric sensing level placement on flash memory,” in Proc. Design Autom. Conf., 2017, pp. 560–565.
[15]
K. Zhao, W. Zhao, H. Sun, T. Zhang, and N. Zheng, “LDPC-in-SSD: Making advanced error correction codes work effectively in solid state drives,” in Proc. 11th USENIX Conf. File Storage Technol., 2013, pp. 1–9.
[16]
S. Ouyang, G. Han, F. Yi, and W. Liu, “LLR-distribution-based non-uniform quantization for RBI-MSD algorithm in MLC flash memory,” IEEE Commun. Lett., vol. 22, no. 1, pp. 45–48, Jan. 2018.
[17]
G. Yadgar, M. Gabel, S. Jaffer, and B. Schroeder, “SSD-based workload characteristics and their performance implications,” ACM Trans. Storage, vol. 17, no. 1, pp. 1–26, 2021.
[18]
M. Zhang, F. Wu, Y. Du, W. Liu, and C. Xie, “Pair-bit errors aware LDPC decoding in MLC NAND flash memory,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 38, no. 12, pp. 2312–2320, Dec. 2019.
[19]
G. Kong, T. Kim, W. Xi, and S. Choi, “Cell-to-cell interference compensation schemes using reduced symbol pattern of interfering cells for MLC NAND flash memory,” in Proc. Asia–Pac. Magn. Record. Conf. (APMRC), 2012, pp. 1–5.
[20]
T. M. Cover and J. A. Thomas, “Elements of information theory; second edition,” Publ. Amer. Stat. Assoc., vol. 103, no. 481, p. 429, 1992.
[21]
G. Dong, N. Xie, and T. Zhang, “On the use of soft-decision error-correction codes in nand flash memory,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 2, pp. 429–439, Feb. 2011.
[22]
C. E. Shannon and C. E. Shannon, The Mathematical Theory of Communication. Urbana, IL, USA: Univ. Illinois Press, 1949.
[23]
T. Tian, C. R. Jones, J. D. Villasenor, and R. D. Wesel, “Selective avoidance of cycles in irregular LDPC code construction,” IEEE Trans. Commun., vol. 52, no. 8, pp. 1242–1247, Aug. 2004.
[24]
Y. J. Ko and J. H. Kim, “Girth conditioning for construction of short block length irregular LDPC codes,” Electron. Lett., vol. 40, no. 3, pp. 187–188, 2004.
[25]
L. Lan, L. Q. Zeng, Y. Y. Tai, S. Lin, and K. Abdelghaffar, “Constructions of quasi-cyclic LDPC codes for the awgn and binary erasure channels based on finite fields and affine mappings,” in Proc. Int. Symp. Inf. Theory, 2005, pp. 1–9.
[26]
D. A. Baglee, “Characteristics and reliability of 100 oxides,” in Proc. 22nd Int. Rel. Phys. Symp., 2007, pp. 152–155.
[27]
Y. Cai, Y. Luo, E. F. Haratsch, K. Mai, and O. Mutlu, “Data retention in MLC NAND flash memory: Characterization, optimization, and recovery,” in Proc. Int. Symp. High Perform. Comput. Archit., 2015, p. 63.
[28]
C. Yu, S. Ghose, E. F. Haratsch, Y. Luo, and O. Mutlu, “Error characterization, mitigation, and recovery in flash memory based solid-state drives,” Proc. IEEE, vol. 105, no. 9, pp. 1666–1704, Sep. 2017.
[29]
“IoTTA.” Accessed: 2021. [Online]. Available: https://iotta.snia.org/traces/list/BlockIO
[30]
“UMass trace repository.” 2013. [Online]. Available: https://traces.cs.umass.edu
Recommendations
A low-complexity coding method for mitigating retention errors and read-disturb errors in TLC NAND flash memory
RACS '22: Proceedings of the Conference on Research in Adaptive and Convergent SystemsWhen the P/E cycles of TLC NAND flash memory is exceeding its limit, data can only be safely stored in the TLC NAND flash memory for a limited retention time or a limited read cycles. As the retention time or the read cycles increases beyond a certain ...
Interleaved LDPC Decoding Scheme Improves 3-D TLC NAND Flash Memory System Performance
Although NAND flash memory does a lot of work in effectively using error correcting code (ECC) to reduce uncorrectable bit error rate (UBER). However, if the frame error rate (FER) is not reduced, the lower UBER cannot effectively reduce the read latency ...
A Dynamic Huffman Coding Method for Reliable TLC NAND Flash Memory
With the progress of the manufacturing process, NAND flash memory has evolved from the single-level cell and multi-level cell into the triple-level cell (TLC). NAND flash memory has physical problems such as the characteristic of erase-before-write and ...
Comments
Information & Contributors
Information
Published In
1937-4151 © 2022 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See https://www.ieee.org/publications/rights/index.html for more information.
Publisher
IEEE Press
Publication History
Published: 01 May 2023
Qualifiers
- Research-article
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 0Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0
Reflects downloads up to 25 Dec 2024