research-article

The warp computer: Architecture, implementation, and performance

Authors:

M. LamAuthors Info & Claims

IEEE Transactions on Computers, Volume 36, Issue 12

Pages 1523 - 1538

https://doi.org/10.1109/TC.1987.5009502

Published: 01 December 1987 Publication History

Abstract

The Warp machine is a systolic array computer of linearly connected cells, each of which is a programmable processor capable of performing 10 million floating-point operations per second (10 MFLOPS). A typical Warp array includes ten cells, thus having a peak computation rate of 100 MFLOPS. The Warp array can be extended to include more cells to accommodate applications capable of using the increased computational bandwidth. Warp is integrated as an attached processor into a Unix host system. Programs for Warp are written in a high-level language supported by an optimizing compiler. The first ten-cell prototype was completed in February 1986; delivery of production machines started in April 1987. Extensive experimentation with both the prototype and production machines has demonstrated that the Warp architecture is effective in the application domain of robot navigation as well as in other fields such as signal processing, scientific computation, and computer vision research. For these applications, Warp is typically several hundred times faster than a VAX 11/780 class computer. This paper describes the architecture, implementation, and performance of the Warp machine. Each major architectural decision is discussed and evaluated with system, software, and application considerations. The programming model and tools developed for the machine are also described. The paper concludes with performance data for a large number of applications.

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Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 36, Issue 12

Dec. 1987

145 pages

ISSN:0018-9340

Editor:
Bruce D. Shriver

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Copyright © 1987.

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 December 1987

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Cited By

Wang DLou JJin NMascarenhas EMahapatra RKinzer SGhodrati SYazdanbakhsh AEsmaeilzadeh HKim NSolihin YHeinrich M(2023)MESA: Microarchitecture Extensions for Spatial Architecture GenerationProceedings of the 50th Annual International Symposium on Computer Architecture10.1145/3579371.3589084(1-14)Online publication date: 17-Jun-2023
https://dl.acm.org/doi/10.1145/3579371.3589084
Weng JLiu SDadu VWang ZShah PNowatzki TMartínez JDuato JEeckhout L(2020)DSAGENProceedings of the ACM/IEEE 47th Annual International Symposium on Computer Architecture10.1109/ISCA45697.2020.00032(268-281)Online publication date: 30-May-2020
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Hughey RBlas A(2008)Finding the Next Computational ModelJournal of Signal Processing Systems10.1007/s11265-007-0130-153:1-2(171-186)Online publication date: 1-Nov-2008
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Taylor MLee WMiller JWentzlaff DBratt IGreenwald BHoffmann HJohnson PKim JPsota JSaraf AShnidman NStrumpen VFrank MAmarasinghe SAgarwal A(2004)Evaluation of the Raw MicroprocessorACM SIGARCH Computer Architecture News10.1145/1028176.100673332:2(2)Online publication date: 2-Mar-2004
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Taylor MKim JMiller JWentzlaff DGhodrat FGreenwald BHoffman HJohnson PLee JLee WMa ASaraf ASeneski MShnidman NStrumpen VFrank MAmarasinghe SAgarwal A(2002)The Raw MicroprocessorIEEE Micro10.1109/MM.2002.99787722:2(25-35)Online publication date: 1-Mar-2002
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