tutorial

Calculating Architectural Vulnerability Factors for Spatial Multi-bit Transient Faults

Authors:

Mark Wilkening,

Vilas Sridharan,

Fritz Previlon,

Sudhanva Gurumurthi,

David R. KaeliAuthors Info & Claims

MICRO-47: Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture

Pages 293 - 305

https://doi.org/10.1109/MICRO.2014.15

Published: 13 December 2014 Publication History

Abstract

Reliability is an important design constraint in modern microprocessors, and one of the fundamental reliability challenges is combating the effects of transient faults. This requires extensive analysis, including significant fault modelling allow architects to make informed reliability tradeoffs. Recent data shows that multi-bit transient faults are becoming more common, increasing from 0.5% of static random-access memory (SRAM) faults in 180nm to 3.9% in 22nm. Such faults are predicted to be even more prevalent in smaller technology nodes. Therefore, accurately modeling the effects of multi-bit transient faults is increasingly important to the microprocessor design process.

Architecture vulnerability factor (AVF) analysis is a method to model the effects of single-bit transient faults. In this paper, we propose a method to calculate AVFs for spatial multibittransient faults (MB-AVFs) and provide insights that can help reduce the impact of these faults. First, we describe a novel multi-bit AVF analysis approach for detected uncorrected errors (DUEs) and show how to measure DUE MB-AVFs in a performance simulator. We then extend our approach to measure silent data corruption (SDC) MB-AVFs. We find that MB-AVFs are not derivable from single-bit AVFs. We also find that larger fault modes have higher MB-AVFs. Finally, we present a case study on using MB-AVF analysis to optimize processor design, yielding SDC reductions of 86% in a GPU vector register file.

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Cited By

Jaulmes LMoretó MValero MErez MCasas MCuicchi CQualters IKramer W(2020)Runtime-guided ECC protection using online estimation of memory vulnerabilityProceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis10.5555/3433701.3433802(1-14)Online publication date: 9-Nov-2020
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Index Terms

Calculating Architectural Vulnerability Factors for Spatial Multi-bit Transient Faults
1. Computer systems organization
  1. Architectures
2. Hardware

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cover image ACM Conferences

MICRO-47: Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture

December 2014

697 pages

ISBN:9781479969982

General Chair:
Krisztian Flautner
ARM
,
Program Chairs:
Thomas F. Wenisch
University of Michigan
,
Emre Ozer
ARM
,
Publications Chair:
Michael Ferdman
Stony Brook University

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IEEE Computer Society

United States

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Published: 13 December 2014

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MICRO-47: The 47th Annual IEEE/ACM International Symposium of Microarchitecture

December 13 - 17, 2014

Cambridge, United Kingdom

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MICRO-47 Paper Acceptance Rate 53 of 279 submissions, 19%;

Overall Acceptance Rate 484 of 2,242 submissions, 22%

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Cited By

Jaulmes LMoretó MValero MErez MCasas MCuicchi CQualters IKramer W(2020)Runtime-guided ECC protection using online estimation of memory vulnerabilityProceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis10.5555/3433701.3433802(1-14)Online publication date: 9-Nov-2020
https://dl.acm.org/doi/10.5555/3433701.3433802
Guo LLi DLaguna ISchulz M(2018)FlipTrackerProceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis10.5555/3291656.3291667(1-14)Online publication date: 11-Nov-2018
https://dl.acm.org/doi/10.5555/3291656.3291667
Guo LLi DLaguna ISchulz M(2018)FlipTrackerProceedings of the International Conference for High Performance Computing, Networking, Storage, and Analysis10.1109/SC.2018.00011(1-14)Online publication date: 11-Nov-2018
https://dl.acm.org/doi/10.1109/SC.2018.00011
Subramaniyan ARehman SShafique MKumar AHenkel J(2017)Soft error-aware architectural exploration for designing reliability adaptive cache hierarchies in multi-coresProceedings of the Conference on Design, Automation & Test in Europe10.5555/3130379.3130388(37-42)Online publication date: 27-Mar-2017
https://dl.acm.org/doi/10.5555/3130379.3130388
Hong JKim S(2017)Smart ECC Allocation Cache Utilizing Cache Data SpaceIEEE Transactions on Computers10.1109/TC.2016.259557066:2(368-374)Online publication date: 1-Feb-2017
https://dl.acm.org/doi/10.1109/TC.2016.2595570
Gebregiorgis AKiamehr SOboril FBishnoi RTahoori MFanucci LTeich J(2016)A cross-layer analysis of soft error, aging and process variation in near threshold computingProceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2971854(205-210)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2971854
Li TAmbrose JRagel RParameswaran S(2016)Processor Design for Soft ErrorsACM Computing Surveys10.1145/299635749:3(1-44)Online publication date: 8-Nov-2016
https://dl.acm.org/doi/10.1145/2996357
Kriebel FRehman SSubramaniyan AAhandagbe SShafique MHenkel J(2016)Reliability-Aware Adaptations for Shared Last-Level Caches in Multi-CoresACM Transactions on Embedded Computing Systems10.1145/296105915:4(1-26)Online publication date: 1-Sep-2016
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Manoochehri MDubois M(2016)Accurate Model for Application Failure Due to Transient Faults in CachesIEEE Transactions on Computers10.1109/TC.2015.248864265:8(2397-2410)Online publication date: 1-Aug-2016
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Ebrahimi MSayed NRashvand MTahoori MNicolescu GGerstlauer A(2015)Fault injection acceleration by architectural importance samplingProceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis10.5555/2830840.2830863(212-219)Online publication date: 4-Oct-2015
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