research-article

EZ-Pass: An Energy & Performance-Efficient Power-Gating Router Architecture for Scalable NoCs

Authors:

Ahmed LouriAuthors Info & Claims

IEEE Computer Architecture Letters, Volume 17, Issue 1

Pages 88 - 91

https://doi.org/10.1109/LCA.2017.2783918

Published: 01 January 2018 Publication History

Abstract

With technology scaling into nanometer regime, static power is becoming the dominant factor in the overall power consumption of Network-on-Chips (NoCs). Static power can be reduced by powering off routers during consecutive idle time through power-gating techniques. However, power-gating techniques suffer from a large wake-up latency to wake up the powered-off routers. Recent research aims to improve the wake-up latency penalty by hiding it through early wake-up techniques. However, these techniques do not exploit the full advantage of power-gating due to the early wake-up. Consequently, they do not achieve significant power savings. In this paper, we propose an architecture called Easy Pass (EZ-Pass) router that remedies the large wake-up latency overheads while providing significant static power savings. The proposed architecture takes advantage of idle resources in the network interface to transmit packets without waking up the router. Additionally, the technique hides the wake-up latency by continuing to provide packet transmission during the wake-up phase. We use full system simulation to evaluate our EZ-Pass router on a 64-core NoC with a mesh topology using PARSEC benchmark suites. Our results show that the proposed router reduces static power by up to 31 percent and overall network latency by up to 32 percent as compared to early-wakeup optimized power-gating techniques.

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Cited By

Ouyang YYuan SLi JLiang H(2024)F-Bypass: A Low-Power Network-on-Chip Design Utilizing Bypass to Improve Network ConnectivityACM Journal on Emerging Technologies in Computing Systems10.1145/369587420:4(1-26)Online publication date: 19-Sep-2024
https://dl.acm.org/doi/10.1145/3695874
Momeni MShahhoseini H(2022)Energy efficient 3D network-on-chip based on approximate communicationComputer Networks: The International Journal of Computer and Telecommunications Networking10.1016/j.comnet.2021.108652203:COnline publication date: 11-Feb-2022
https://dl.acm.org/doi/10.1016/j.comnet.2021.108652
Chen YLouri AEigenmann RDing CMcKee S(2019)An online quality management framework for approximate communication in network-on-chipsProceedings of the ACM International Conference on Supercomputing10.1145/3330345.3330365(217-226)Online publication date: 26-Jun-2019
https://dl.acm.org/doi/10.1145/3330345.3330365
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EZ-Pass: An Energy & Performance-Efficient Power-Gating Router Architecture for Scalable NoCs
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cover image IEEE Computer Architecture Letters

IEEE Computer Architecture Letters Volume 17, Issue 1

January 2018

99 pages

ISSN:1556-6056

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Copyright © 2018.

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IEEE Computer Society

United States

Publication History

Published: 01 January 2018

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Cited By

Ouyang YYuan SLi JLiang H(2024)F-Bypass: A Low-Power Network-on-Chip Design Utilizing Bypass to Improve Network ConnectivityACM Journal on Emerging Technologies in Computing Systems10.1145/369587420:4(1-26)Online publication date: 19-Sep-2024
https://dl.acm.org/doi/10.1145/3695874
Momeni MShahhoseini H(2022)Energy efficient 3D network-on-chip based on approximate communicationComputer Networks: The International Journal of Computer and Telecommunications Networking10.1016/j.comnet.2021.108652203:COnline publication date: 11-Feb-2022
https://dl.acm.org/doi/10.1016/j.comnet.2021.108652
Chen YLouri AEigenmann RDing CMcKee S(2019)An online quality management framework for approximate communication in network-on-chipsProceedings of the ACM International Conference on Supercomputing10.1145/3330345.3330365(217-226)Online publication date: 26-Jun-2019
https://dl.acm.org/doi/10.1145/3330345.3330365
Zheng HLouri A(2019)An Energy-Efficient Network-on-Chip Design using Reinforcement LearningProceedings of the 56th Annual Design Automation Conference 201910.1145/3316781.3317768(1-6)Online publication date: 2-Jun-2019
https://dl.acm.org/doi/10.1145/3316781.3317768
Wang KLouri AKaranth ABunescu RManne SHunter HAltman E(2019)IntelliNoCProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322274(589-600)Online publication date: 22-Jun-2019
https://dl.acm.org/doi/10.1145/3307650.3322274
Zhao XAdileh AYu ZWang ZJaleel AEeckhout LManne SHunter HAltman E(2019)Adaptive memory-side last-level GPU cachingProceedings of the 46th International Symposium on Computer Architecture10.1145/3307650.3322235(411-423)Online publication date: 22-Jun-2019
https://dl.acm.org/doi/10.1145/3307650.3322235

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