research-article

Gate-level netlist reverse engineering for hardware security: Control logic register identification

Authors:

Travis Meade,

Yier Jin,

Mark Tehranipoor,

Shaojie ZhangAuthors Info & Claims

2016 IEEE International Symposium on Circuits and Systems (ISCAS)

Pages 1334 - 1337

https://doi.org/10.1109/ISCAS.2016.7527495

Published: 01 May 2016 Publication History

Abstract

The heavy reliance on third-party resources, including third-party IP cores and fabrication foundries, has triggered the security concerns that design backdoors and/or hardware Trojans may be inserted into fabricated chips. While existing reverse engineering tools can help recover netlist from fabricated chips, there is a lack of efficient tools to further analyze the netlist for malicious logic detection and full functionality recovery. While it is relatively easy to identify the functional modules from the netlist using pattern matching methods, the main obstacle is to isolate control logic registers and reverseengineering the control logic. Upon this request, we proposed a topology-based computational method for register categorization. Through this proposed algorithm, we can differentiate data registers from control logic registers such that the control logic can be separated from the datapath. Experimental results showed that the suggested method was capable of identifying control logic registers in circuits with various complexities ranging from the RS232 core to the 8051 microprocessor.

References

[1]

Http://www.adnas.com/.

Google Scholar

[2]

M. Oya, Y. Shi, M. Yanagisawa, and N. Togawa, “A score-based classifiication method for identifying hardware-trojans at gate-level netlists,” in 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), ser. DATE'15, 2015, pp. 465–470.

Google Scholar

[3]

X. Zhang and M. Tehranipoor, “Case study: Detecting hardware trojans in third-party digital ip cores,” in Hardware-Oriented Security and Trust (HOST), 2011 IEEE International Symposium on, 2011, pp. 67–70.

Google Scholar

[4]

F. Koushanfar and A. Mirhoseini, “A unified framework for multimodal submodular integrated circuits trojan detection,” IEEE Transactions on Information Forensics and Security, vol. 6, no. 1, pp. 162–174, 2011.

Digital Library

Google Scholar

[5]

Http://www.chipworks.com/.

Google Scholar

[6]

W. Li, A. Gascon, P. Subramanyan, W. Y. Tan, A. Tiwari, S. Malik, N. Shankar, and S. Seshia, “Wordrev: Finding word-level structures in a sea of bit-level gates,” in Hardware-Oriented Security and Trust (HOST), 2013 IEEE International Symposium on, 2013, pp. 67–74.

Google Scholar

[7]

Y. Shi, C. W. Ting, B.-H. Gwee, and Y. Ren, “A highly efficient method for extracting fsms from flattened gate-level netlist,” in Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, 2010, pp. 2610–2613.

Google Scholar

[8]

T. Meade, S. Zhang, and Y. Jin, “Netlist reverse engineering for high-level functionality reconstruction,” in Asia and South Pacific Design Automation Conference (ASP-DAC), 2016, pp. 655–660.

Google Scholar

[9]

K. S. McElvain, “Methods and apparatuses for automatic extraction of finite state machines,” U.S. Patent 6182 268, 2001.

Google Scholar

[10]

W. Li, Z. Wasson, and S. Seshia, “Reverse engineering circuits using behavioral pattern mining,” in Hardware-Oriented Security and Trust (HOST), 2012 IEEE International Symposium on, 2012, pp. 83–88.

Google Scholar

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2016 IEEE International Symposium on Circuits and Systems (ISCAS)

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Published: 01 May 2016

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Rahman MGeist JXing DLiu YSrivastava AMeade TJin YBhunia S(2024)Security Evaluation of State Space Obfuscation of Hardware IP through a Red Team-Blue Team PracticeACM Transactions on Design Automation of Electronic Systems10.1145/364046129:3(1-18)Online publication date: 5-Mar-2024
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References

Cited By

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