A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper
Pages 1014 - 1017
Abstract
We propose a data-aware power cut-off write-assist 12T SRAM cell (DPC12T) which improves the write-ability to improve the write minimum operating voltage (VMIN). Moreover, we propose an adaptive data-aware keeper (DAK) to lower the design conflicts among the keeper current, read current and the bit-line leakage current to improve the read stability and read VMIN for single-ended read operation. Fabricated 40nm 8kb test chip macro with 64 cells per bit-line can achieve VMIN 250 mV and 230 mV without and with enabling DAK at 6 MHz and 4 MHz, respectively. The SRAM test macro with 256, 512 and 1024 cells per bit-line demonstrates that DAK improves the read VMIN by 9% to 21% at low supply voltages.
References
[1]
S. Yoshimoto et al., “A 40-nm 0.5-V $20.1-\mu \mathrm{W}/\mathrm{MHz}$ 8T SRAM with low-energy disturb mitigation scheme,” in Symp. VLSI Technology, Jun. 2011, pp. 72–73.
[2]
J. Kulkarni et al., “Dual-VCC 8T-bitcell SRAM array in 22nm tri-gate CMOS for energy-efficient operation across wide dynamic voltage range,” in Symp. VLSI Circuits, Jun. 2013, pp. C126–C127.
[3]
Yen-Huei Chen, et al., “A 16nm 128Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-Vmin applications,” in IEEE Int. Solid-State Circuits Conf., Feb. 2014, pp. 238–239.
[4]
O. Hirabayashi et al., “A process-variation-tolerant dual-power-supply SRAM with $0.179\ \mu \mathrm{m}^{2}$ cell in 40nm CMOS using level-programmable wordline driver,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2009, pp. 458–459, 459a.
[5]
E. Karl et al., “A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry,” in IEEE Int. Solid-State Circuits Conf., Feb. 2012, pp. 230–232.
[6]
A. J. Bhavnagarwala et al., “A sub-600-mv, fluctuation tolerant 65-nm cmos sram array with dynamic cell biasing,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 946–955, Apr. 2008.
[7]
M. H. Tu et al., “Single-ended subthreshold SRAM with asymmetrical write/read-assist,” IEEE Trans. Circuits Syst. I, vol. 57, no. 12, pp. 3039–3047, Dec. 2010.
[8]
T. Song et al., “13.2 a 14nm finfet 128mb 6t sram with vmin-enhancement techniques for low-power applications,” in IEEE Int. Solid-State Circuits Conf., Feb. 2014, pp. 232–233.
[9]
K. Kushida et al., “A 0.7 V single-supply SRAM with $0.495\ \mu \mathrm{m}^{2}$ cell in 65 nm technology utilizing self-write-back sense amplifier and cascaded bit line scheme,” IEEE J. Solid-State Circuits, vol. 44, no. 4, pp. 1192–1198, Apr. 2009.
[10]
I. J. Chang et al., “A 32 kb 10T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm cmos,” IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 650–658, Feb. 2009.
[11]
N, Verma, et al., “A 256 kb 65 nm 8T subthreshold SRAM employing sense-amplifier redundancy,” IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 141–149, Mon. 2008.
[12]
Y. W. Chiu et al., “40nm bit-interleaving 12T subthreshold SRAM with data-aware write-assist,” IEEE Trans. Circuits Syst. I, vol. 61, no. 9, pp. 2578–2585, Sep. 2014.
Recommendations
Comments
Information & Contributors
Information
Published In
2904 pages
Copyright © 2016.
Publisher
IEEE Press
Publication History
Published: 01 May 2016
Qualifiers
- Research-article
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 0Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0
Reflects downloads up to 30 Dec 2024