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- Borrione DHelmy APierre LSchmaltz J(2009)A formal approach to the verification of networks on chipEURASIP Journal on Embedded Systems10.1155/2009/5483242009(1-14)Online publication date: 1-Jan-2009
- Garavel HSalaün GSerwe W(2009)On the semantics of communicating hardware processes and their translation into LOTOS for the verification of asynchronous circuits with CADPScience of Computer Programming10.1016/j.scico.2008.09.01174:3(100-127)Online publication date: 1-Jan-2009
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