research-article

Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design

Authors:

Chien-In Henry Chen,

Joel T. YuenAuthors Info & Claims

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 2, Issue 3

Pages 273 - 291

https://doi.org/10.1109/92.311637

Published: 01 September 1994 Publication History

Abstract

Built-In Self Test (BIST) has been proposed as a powerful technique for addressing the highly complex testing problems of VLSI circuits. In the BIST methodology, two major problems which must be addressed are test generation and response analysis. In this paper, we present an efficient unified procedure, named Three-Phase cluster partitioning, to automatically synthesize a pseudo-exhaustive test generator for VLSI BIST design. Previous approaches to the problem of test generation have optimized computational efficiency at the expense of the required hardware overhead, or vice versa. Our design procedure is computationally efficient and produces test generation circuitry with low hardware overhead. The procedure minimizes the number of test patterns that are required for pseudo-exhaustive test. Based on Three-Phase Cluster Partitioning, a design generator named BISTSYN has been developed and implemented to facilitate the BIST design. The input to the design generator is a circuit description at the gate level which is viewed as a netlist. BISTSYN provides the BIST mechanisms as the output. For those conventional circuits which are extremely unsuitable for pseudo-exhaustive test, BISTSYN employs a circuit partitioning tool, named Autonomous, to partition the combinational portion of the circuit into different structural subcircuits so that each subcircuit can be pseudo-exhaustively tested. We demonstrate the effectiveness of BISTSYN by applying the method to different examples and practical VLSI designs. The detailed comparisons of our benchmark simulation results against those that would be obtained by existing techniques are also presented.

References

[1]

T. W. Williams and K. P. Parker, "Design for testability-A survey," IEEE Trans. Comput., vol. C-31, pp. 2-15, Jan. 1982.

[2]

E. J. McCluskey, "Built-in self test techniques," IEEE Design and Test of Comput., pp. 21-28, Apr. 1985.

Digital Library

[3]

V. K. Agrawal and E. Cemey, "Store and generate built--In testing approach," Proc. 11th Int. Symp. Fault-Tolerant Computing, pp. 3540, 1981.

[4]

D. Komonystky, "LSI self-test using LSSD and signature analysis," Proc. Int. Test Conf., pp. 414-424, 1982.

[5]

Y. M. El-Zig, "S₃ : VLSI self-testing using a signature analysis and scan-path techniques," Proc. Inc. Conf., Computer-Aided Design, pp. 73-76, 1983.

[6]

P. H. Bardell and W. H. McAnney, "Self-testing of multichip logic modules," Proc. Int. Test Conf., pp. 200-204, 1982.

[7]

P. P. Fasang, "BIDCO, built-in digital circuit observer," Proc. Inc. Test Conf., pp. 261-266, 1980.

[8]

A. Kransniewski and A. Albicki, "Automatic design of exhaustively selftesting chips with BIBLO modules," Proc. Int. Test Conf., pp. 362-371, 1985.

[9]

B. Koenemann et al., "Built-in logic block observation techniques," Proc. Int. Test Conf., pp. 37-41, 1979.

[10]

Z. Barzilai, J. Savir, G. Markowsky, and M. G. Smith, "The weighted syndrome sums approach to VLSI testing," IEEE Trans. Comput., vol. C-29, pp. 1012-1013, NOV. 1981.

[11]

E. J. McCluskey, "Verification testing--A pseudoexhaustive test technique," IEEE Trans. Comput., vol. C-33, no. 6, June 1984.

[12]

S. B. Akers, "On the use of linear sums in exhaustive testing," Proc. 15th Fault Tolerant Comp. Symp., pp. 148-153, June 1985.

[13]

N. Vasanthavada and P. N. Marinos, "An operationally efficient scheme for exhaustive test-pattem generation using linear codes," Proc. 1985, IEEE Test Conf., pp. 476-482, 1985.

[14]

L. T. Wang and E. J. McCluskey, "Condensed linear feedback shifter register (LFSR) testing--A pseudoexhaustive test technique," IEEE Trans. Compur., vol. C-35, no. 4, 1986.

[15]

L. T. Wang and E. J. McCluskey, "Circuits for pseudo-exhaustive test pattern generation," Proc. 1986 IEEE Inr. Tesr Conf., pp. 25-37, 1986.

[16]

W. W. Peterson and E. J. Weldon, Jr., Error Correcting Codes. Cambridge, MA: MIT Press, 2nd edition, 1972.

[17]

C.-I. H. Chen and J. Yuen, "Autonomous--Tool for hardware parttioning in a built-in self-test environment," Proc. of IEEE Int. Conf. on Computer Design, pp. 264-267, 1992.

[18]

F. Brglez, P. Pownall, and R. Hum, "Accelerated ATPG and fault grading via testability analysis," Proc. IEEE Int. Symp. Circ. and Syst., pp. 695-698, 1985.

[19]

H. Fujiwara and T. Shimono, "On the acceleration of test generation algorithms," IEEE Trans. Comput., vol. C-32, pp. 1137-1144, 1983.

[20]

W.-T. Cheng and M.-L. Yu. "Differential fault simulation--A fast method using minimal memory," Proc. 26th Design Automat. Conf., pp. 424-428, 1989.

[21]

W.-T. Cheng and T. J. Lewandowski, "GENTEST, an automatic test generation system for sequential circuits," Comput. Mag., Apr. 1989.

[22]

S. B. Akers and W. Jansz, "Test set embedding in a built-in self-test environment," Proc. 1989 Int. Test Cof., pp. 257-263, 1989.

[23]

R. D. Dixon, M. Calle, C. W. Longway, L. Peterson, and R. Siferd, "The SFl real time computer," Proc. IEEE Nat'l Aerospace and Electron. Conf., pp. 60-64, 1988.

[24]

G. Kane, MIPS RISC Architecture. Englewood Cliffs, NJ: Prentice Hall, 1988.

[25]

E. Reingold, J. Nievergelt, and N. Deo, Combinatorial Algorithms: Theory and Practice. Englewood Cliffs, NJ: Prentice-Hall, 1977, pp. 353-354.

Cited By

Noh JPark CRhee K(2004)Path sensitization and sub-circuit partition of CUT using t,-distribution for pseudo-exhaustive testingProceedings of the Third Asian simulation conference on Systems Modeling and Simulation: theory and applications10.1007/978-3-540-30585-9_23(205-213)Online publication date: 4-Oct-2004
https://dl.acm.org/doi/10.1007/978-3-540-30585-9_23
Chen CHermida RAboulhamid E(2001)Synthesis of configurable linear feedback shifter registers for detecting random-pattern-resistant faultsProceedings of the 14th international symposium on Systems synthesis10.1145/500001.500051(203-208)Online publication date: 30-Sep-2001
https://dl.acm.org/doi/10.1145/500001.500051
Mukherjee NRajski JTyszer J(2001)Testing Schemes for FIR Filter StructuresIEEE Transactions on Computers10.1109/12.93623450:7(674-688)Online publication date: 1-Jul-2001
https://dl.acm.org/doi/10.1109/12.936234
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Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design
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Published In

cover image IEEE Transactions on Very Large Scale Integration (VLSI) Systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems Volume 2, Issue 3

September 1994

113 pages

ISSN:1063-8210

Issue’s Table of Contents

Copyright © 1994.

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IEEE Educational Activities Department

United States

Publication History

Published: 01 September 1994

Revised: 02 April 1993

Received: 07 October 1992

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Cited By

Noh JPark CRhee K(2004)Path sensitization and sub-circuit partition of CUT using t,-distribution for pseudo-exhaustive testingProceedings of the Third Asian simulation conference on Systems Modeling and Simulation: theory and applications10.1007/978-3-540-30585-9_23(205-213)Online publication date: 4-Oct-2004
https://dl.acm.org/doi/10.1007/978-3-540-30585-9_23
Chen CHermida RAboulhamid E(2001)Synthesis of configurable linear feedback shifter registers for detecting random-pattern-resistant faultsProceedings of the 14th international symposium on Systems synthesis10.1145/500001.500051(203-208)Online publication date: 30-Sep-2001
https://dl.acm.org/doi/10.1145/500001.500051
Mukherjee NRajski JTyszer J(2001)Testing Schemes for FIR Filter StructuresIEEE Transactions on Computers10.1109/12.93623450:7(674-688)Online publication date: 1-Jul-2001
https://dl.acm.org/doi/10.1109/12.936234
Rajski JTamarapalli NTyszer J(1998)Automated synthesis of large phase shifters for built-in self-testProceedings of the 1998 IEEE International Test Conference10.5555/648020.761109(1047-1056)Online publication date: 18-Oct-1998
https://dl.acm.org/doi/10.5555/648020.761109
Jone WRau JChang SWu Y(1998)A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuitsProceedings of the 1998 IEEE International Test Conference10.5555/648020.745632(322-330)Online publication date: 18-Oct-1998
https://dl.acm.org/doi/10.5555/648020.745632
Gupta SRajski JTyszer J(1996)Arithmetic Additive Generators of Pseudo-Exhaustive Test PatternsIEEE Transactions on Computers10.1109/12.53623645:8(939-949)Online publication date: 1-Aug-1996
https://dl.acm.org/doi/10.1109/12.536236

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