Implementing scheduling algorithms in high-speed networks

The fluid generalized processor sharing (GPS) algorithm has desirable properties for integrated services networks and many packet fair queueing (PFQ) algorithms have been proposed to approximate GPS. However, there have been few high-speed implementations of PFQ algorithms that can support a large number of sessions with diverse rate requirements and at the same time maintain all the important properties of GPS. The implementation cost of a PFQ algorithm is determined by: (1) computation of the system virtual time function; (2) maintenance of the relative ordering of the packets via their timestamps (scheduling); and (3) regulation of packets based on eligibility time, in some algorithms. While most of the recently proposed PFQ algorithms reduce the complexity of computing the system virtual time function, the complexity of scheduling and traffic regulation is still a function of the number of active sessions. In addition, while reducing the algorithmic or asymptotic complexity has been the focus of most analysis, it is also important to reduce the complexity of basic operations in order for the algorithm to run at high speed. We develop techniques to reduce both types of complexities for networks of both fixed and variable size packets. Regulation and scheduling are implemented in an integrated architecture that can be viewed as logically performing sorting in two dimensions simultaneously. By using a novel grouping architecture, we are able to perform this with an algorithmic complexity independent of the number of sessions in the system at the cost of a small controllable amount of relative error. To reduce the cost of basic operations, we propose a hardware-implementation framework and several novel techniques that reduce the on-chip memory size, off-chip memory bandwidth, and off-chip access latency. The proposed implementation techniques have been incorporated into commercial ATM switch and IP router products