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The Virtual Interface Architecture

Published: 01 March 1998 Publication History

Abstract

Network bandwidths have been increasing and latencies through these networks have been decreasing. Unfortunately, applications have not been able to take full advantage of these performance improvements due to the many layers of user level and kernel level software that is required to get to the network. The Virtual Interface Architecture (or simply VI Architecture) was developed to significantly reduce the software overhead between a high performance CPU/memory subsystem and a high performance network. The Virtual Interface Architecture defines a set of functions and associated semantics used for moving data into and out of a process' memory. The design focus of the VI Architecture is to achieve low latency, high bandwidth communication/data exchange between processes running on two nodes within a computing cluster, with minimal CPU usage. Low latency and sustained high bandwidth are achieved by allowing a user process direct access to the network interface, avoiding intermediate copies of data and bypassing the operating system in a fully-protected fashion. CPU utilization is minimized by avoiding interrupts and context switches whenever possible. This article presents the mechanisms which support protected, zero-copy user-level access and the performance data of one implementation of the VI Architecture. Intel Corporation, Compaq Computer Corporation and Microsoft Corporation jointly authored the VI Architecture specification. A copy of the specification can be found at http://www.viarch.org/.

References

[1]
R.P. Martin, et al., "Effects of Communication Latency, Overhead and Bandwidth in a Cluster Architecture," Computer Architecture News, May 1997, pp. 85-97.
[2]
R. Gusella, "A Measurement Study of Diskless Workstation Traffic on an Ethernet," IEEE Trans. Communications, Vol. 38, No. 9, Sept. 1990, pp. 1557-1568.
[3]
J. Kay and J. Pasquale, "The Importance of Non-Data Touching Processing Overheads in TCP/IP," Computer Communication Review, Vol. 23, No. 4, Oct. 1993, pp. 259-268.
[4]
D.D. Clark, et al., "An Analysis of TCP Processing Overhead," IEEE Communications, Vol. 27, No. 6, June 1989, pp. 23-29.
[5]
J.L. Hennessy and D.A. Patterson, Computer Architecture: A Quantitative Approach, 2nd. ed., Morgan Kaufmann Publishers, Inc., San Francisco, Calif., 1995.
[6]
G. Buzzard, et al., "An Implementation of the Hamlyn Sender-Managed Interface Architecture," Operating Systems Review, 1996, pp. 245-259.
[7]
T. von Eicken, et al., "U-Net: A User-level Network Interface for Parallel and Distributed Computing," Operating Systems Review, Vol. 29, No. 5, Dec. 1995, pp. 40-53.
[8]
W.J. Dally, et al., "Architecture of a Message-Driven Processor." Proc. 14th Int'l Symp. Computer Architecture, IEEE Computer Society Press, Los Alamitos, Calif., 1987, pp. 189-196.
[9]
T. von Eicken, et al., "Active Messages: a Mechanism for Integrated Communications and Computation," Computer Architecture News, Vol. 20, No. 2, May 1992, pp. 256-266.
[10]
S. Pakin V. Karamcheti and A. Chien, "Fast Messages (FM): Efficient, Portable Communication for Workstations and Massively-Parallel Processors," IEEE Concurrency, Vol. 5, No. 2, Apr.-June 1997, pp. 60-72.
[11]
M.A. Blumrich, et al., "Virtual Memory Mapped Network Interface for the SHRIMP Multicomputer," Proc. 21st Int'l Symp. Computer Architecture, Apr. 1994, pp. 142-153.
[12]
R. Gillett and R. Kaufmann, "Using the Memory Channel Network," IEEE Micro, Vol. 17, No. 1, Jan.-Feb. 1997, pp. 19-25.
[13]
M.L. Bailey, et al., "PathFinder: A Pattern-Based Packet Classifier," Proc. First Symp. Operating Systems Design and Implementation, Usenix Assoc., Sunset Beach, Calif., Nov. 1994, pp. 115-123.
[14]
P. Pierce and G. Regnier, "Fast Messages: Efficient, Portable Communication for Workstation Clusters and MPPs," IEEE Concurrency, Vol. 5, No. 2, Apr.-June 1997, pp. 60-72.

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cover image IEEE Micro
IEEE Micro  Volume 18, Issue 2
March 1998
79 pages

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 March 1998

Author Tags

  1. VI Architecture
  2. data I/O
  3. network interface
  4. networking
  5. software overhead

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