research-article

Tuning the Pentium Pro Microarchitecture

Author:

David B. PapworthAuthors Info & Claims

IEEE Micro, Volume 16, Issue 2

Pages 8 - 15

https://doi.org/10.1109/40.491458

Published: 01 April 1996 Publication History

Publisher Site

Abstract

This inside look at a large microprocessor development project reveals some of the reasoning (for goals, changes, trade-offs, and performance simulation) that lay behind its final form.

References

[1]

R. Colwell and R. Steck, "A 0.6-μm BiCMOS Microprocessor with Dynamic Execution," Proc. Int'l Solid-State Circuits Conf., IEEE, Piscataway, N.J., 1995, pp. 176-177.

Google Scholar

[2]

http://www.intel.com/procs/p6/p6white/index.html (Intel's World Wide Web site).

Google Scholar

[3]

L. Gwennap, "Intel's P6 Uses Decoupled Superscalar Design," Microprocessor Report, Vol. 9, No. 2, Feb. 16, 1995, pp. 9-15.

Google Scholar

Cited By

View all

Zoni DGalimberti AFornaciari W(2023)A Survey on Run-time Power Monitors at the EdgeACM Computing Surveys10.1145/359304455:14s(1-33)Online publication date: 18-Apr-2023
https://dl.acm.org/doi/10.1145/3593044
Golestani HSen RYoung VGupta GRauchwerger LCameron KNikolopoulos DPnevmatikatos D(2022)CalipersProceedings of the 36th ACM International Conference on Supercomputing10.1145/3524059.3532390(1-14)Online publication date: 28-Jun-2022
https://dl.acm.org/doi/10.1145/3524059.3532390
Naffziger SBeck NBurd TLepak KLoh GSubramony MWhite SMartínez JDuato JJohn L(2021)Pioneering chiplet technology and design for the AMD EPYC™ and Ryzen™ processor familiesProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00014(57-70)Online publication date: 14-Jun-2021
https://dl.acm.org/doi/10.1109/ISCA52012.2021.00014
Show More Cited By

Recommendations

Microarchitecture of HaL's CPU
COMPCON '95: Proceedings of the 40th IEEE Computer Society International Conference

The HaL PM1 CPU is the first implementation of the 64-bit SPARC Version 9 instruction set architecture. The processor utilizes superscalar instruction issue, register renaming, and a dataflow model of execution. Instructions can complete out-of-order ...
The Unabridged Pentium 4: IA32 Processor Genealogy
Performance Characterization of the Pentium® Pro Processor
HPCA '97: Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture

In this paper, we characterize the performance of several business and technical benchmarks on a Pentium â Pro processor based system. Various architectural data are collected using a performance monitoring counter tool. Results show that the Pentium ...

Comments

Information & Contributors

Information

Published In

IEEE Micro Volume 16, Issue 2

April 1996

146 pages

ISSN:0272-1732

Issue’s Table of Contents

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 April 1996

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

39
Total Citations
View Citations
0
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 30 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

View all

Zoni DGalimberti AFornaciari W(2023)A Survey on Run-time Power Monitors at the EdgeACM Computing Surveys10.1145/359304455:14s(1-33)Online publication date: 18-Apr-2023
https://dl.acm.org/doi/10.1145/3593044
Golestani HSen RYoung VGupta GRauchwerger LCameron KNikolopoulos DPnevmatikatos D(2022)CalipersProceedings of the 36th ACM International Conference on Supercomputing10.1145/3524059.3532390(1-14)Online publication date: 28-Jun-2022
https://dl.acm.org/doi/10.1145/3524059.3532390
Naffziger SBeck NBurd TLepak KLoh GSubramony MWhite SMartínez JDuato JJohn L(2021)Pioneering chiplet technology and design for the AMD EPYC™ and Ryzen™ processor familiesProceedings of the 48th Annual International Symposium on Computer Architecture10.1109/ISCA52012.2021.00014(57-70)Online publication date: 14-Jun-2021
https://dl.acm.org/doi/10.1109/ISCA52012.2021.00014
Sharafeddin MAkkary H(2015)A small and power efficient checkpoint core architecture for manycore processorsInternational Journal of High Performance Systems Architecture10.1504/IJHPSA.2015.0728525:4(216-227)Online publication date: 1-Nov-2015
https://dl.acm.org/doi/10.1504/IJHPSA.2015.072852
Peir JLai SLu SStark JLai K(2014)Bloom filtering cache misses for accurate data speculation and prefetchingACM International Conference on Supercomputing 25th Anniversary Volume10.1145/2591635.2667183(347-356)Online publication date: 10-Jun-2014
https://dl.acm.org/doi/10.1145/2591635.2667183
Jothi KAkkary H(2014)Tuning the continual flow pipeline architecture with virtual register renamingACM Transactions on Architecture and Code Optimization10.1145/257967511:1(1-27)Online publication date: 1-Feb-2014
https://dl.acm.org/doi/10.1145/2579675
Jothi KAkkary HAyala JJones AMadden PCoskun A(2013)Virtual register renamingProceedings of the 23rd ACM international conference on Great lakes symposium on VLSI10.1145/2483028.2483057(43-48)Online publication date: 2-May-2013
https://dl.acm.org/doi/10.1145/2483028.2483057
Jothi KAkkary HMalony ANemirovsky MMidkiff S(2013)Tuning the continual flow pipeline architectureProceedings of the 27th international ACM conference on International conference on supercomputing10.1145/2464996.2465011(243-252)Online publication date: 10-Jun-2013
https://dl.acm.org/doi/10.1145/2464996.2465011
Sharafeddine MAkkary HCarmean D(2013)Virtual register renamingProceedings of the 26th international conference on Architecture of Computing Systems10.1007/978-3-642-36424-2_8(86-97)Online publication date: 19-Feb-2013
https://dl.acm.org/doi/10.1007/978-3-642-36424-2_8
Sharafeddine MJothi KAkkary H(2012)Disjoint out-of-order execution processorACM Transactions on Architecture and Code Optimization10.1145/2355585.23555929:3(1-32)Online publication date: 5-Oct-2012
https://dl.acm.org/doi/10.1145/2355585.2355592
Show More Cited By

Abstract

References

Cited By

Recommendations

Microarchitecture of HaL's CPU

The Unabridged Pentium 4: IA32 Processor Genealogy

Performance Characterization of the Pentium® Pro Processor

Comments

Information

Published In

Publisher

Publication History

Qualifiers

Contributors

Other Metrics

Bibliometrics

Article Metrics

Other Metrics

Citations

Cited By

View options

Share

Share this Publication link

Share on social media

Affiliations