research-article

Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits

Authors:

Sreejit Chakravarty,

Paul J. ThadikaranAuthors Info & Claims

IEEE Transactions on Computers, Volume 45, Issue 10

Pages 1131 - 1140

https://doi.org/10.1109/12.543707

Published: 01 October 1996 Publication History

Abstract

In the absence of information about the layout, test generation, and fault simulation systems must target all bridging faults. A novel algorithm, that is both time and space efficient, for simulating IDDQTests for all two-line bridging faults in combinational circuits is presented. Simulation results using randomly generated test sets point to the computational feasibility of targeting all two-line bridging faults. On a more theoretical note, we show that: The problem of computing IDDQ tests for all two-line bridging faults, even in some restricted classes of circuits, is intractable; and, even under some pessimistic assumptions, a complete IDDQ test set for all two-line bridging faults also covers all multiple line, single cluster bridging faults.

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Cited By

Koushanfar FMirhoseini AAlkabani Y(2010)A unified submodular framework for multimodal IC Trojan detectionProceedings of the 12th international conference on Information hiding10.5555/1929304.1929306(17-32)Online publication date: 28-Jun-2010
https://dl.acm.org/doi/10.5555/1929304.1929306
Hong YHuang J(2009)Reducing fault dictionary size for million-gate large circuitsACM Transactions on Design Automation of Electronic Systems10.1145/1497561.149757014:2(1-14)Online publication date: 7-Apr-2009
https://dl.acm.org/doi/10.1145/1497561.1497570
Higami YTakamatsu YSaluja KKinoshita KYoshida K(2000)Fault models and test generation for IDDQ testingProceedings of the 2000 Asia and South Pacific Design Automation Conference10.1145/368434.368773(509-514)Online publication date: 28-Jan-2000
https://dl.acm.org/doi/10.1145/368434.368773
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Index Terms

Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits

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Published In

cover image IEEE Transactions on Computers

IEEE Transactions on Computers Volume 45, Issue 10

October 1996

129 pages

ISSN:0018-9340

Editor:
Jane W. S. Liu
Univ. of Illinois, Urbana, IL

Issue’s Table of Contents

Copyright © Copyright © 1996 IEEE. All Rights Reserved.

Publisher

IEEE Computer Society

United States

Publication History

Published: 01 October 1996

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Cited By

Koushanfar FMirhoseini AAlkabani Y(2010)A unified submodular framework for multimodal IC Trojan detectionProceedings of the 12th international conference on Information hiding10.5555/1929304.1929306(17-32)Online publication date: 28-Jun-2010
https://dl.acm.org/doi/10.5555/1929304.1929306
Hong YHuang J(2009)Reducing fault dictionary size for million-gate large circuitsACM Transactions on Design Automation of Electronic Systems10.1145/1497561.149757014:2(1-14)Online publication date: 7-Apr-2009
https://dl.acm.org/doi/10.1145/1497561.1497570
Higami YTakamatsu YSaluja KKinoshita KYoshida K(2000)Fault models and test generation for IDDQ testingProceedings of the 2000 Asia and South Pacific Design Automation Conference10.1145/368434.368773(509-514)Online publication date: 28-Jan-2000
https://dl.acm.org/doi/10.1145/368434.368773
Jiang WVinnakota B(1999)IC test using the energy consumption ratioProceedings of the 36th annual ACM/IEEE Design Automation Conference10.1145/309847.310109(976-981)Online publication date: 1-Jun-1999
https://dl.acm.org/doi/10.1145/309847.310109
Thadikaran PChakravarty SPatel J(1997)Algorithms to compute bridging fault coverage of test setsACM Transactions on Design Automation of Electronic Systems10.1145/264995.2649992:3(281-305)Online publication date: 1-Jul-1997
https://dl.acm.org/doi/10.1145/264995.264999

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