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On minimising the maximum expected verification time

Published: 01 June 2017 Publication History

Abstract

Cyber Physical Systems (CPSs) consist of hardware and software components. To verify that the whole (i.e., software + hardware) system meets the given specifications, exhaustive simulation-based approaches (Hardware In the Loop Simulation, HILS) can be effectively used by first generating all relevant simulation scenarios (i.e., sequences of disturbances) and then actually simulating all of them (verification phase). When considering the whole verification activity, we see that the above mentioned verification phase is repeated until no error is found. Accordingly, in order to minimise the time taken by the whole verification activity, in each verification phase we should, ideally, start by simulating scenarios witnessing errors (counterexamples). Of course, to know beforehand the set of such scenarios is not feasible. In this paper we show how to select scenarios so as to minimise the Worst Case Expected Verification Time. Simulation: main workhorse for System Level Verification of Cyber Physical Systems.A counterexample is a simulation scenario witnessing a design error.WCEVT: max expected number of scenarios simulated before hitting a counterexample.We show that the minimum WCEVT is (n+1)/2 (n number of simulation scenarios).The infinite set of optimal simulation strategies forms a convex bounded polytope.

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Published In

cover image Information Processing Letters
Information Processing Letters  Volume 122, Issue C
June 2017
31 pages

Publisher

Elsevier North-Holland, Inc.

United States

Publication History

Published: 01 June 2017

Author Tags

  1. Explicit model checking
  2. Formal methods
  3. Formal verification
  4. Software engineering
  5. System-level formal verification

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