Transverse dielectric and lateral channel band engineering of drain-side and source-side injection in Ge-based charge-trapping memory cells for energy-efficient applications
Pages 128 - 147
Abstract
Ge is an attractive alternative to replace Si as the body material for scaled CMOS technologies. This work comprehensively investigates hot-electron generation and injection in the Ge-based channel body and gate dielectric charge-trapping memory. This study numerically elucidates the mechanisms of transverse dielectric and lateral channel band engineering used in source-side and drain-side injection. Various Ge- and Si-based cells are compared to determine the optimal low-voltage energy-efficient cells. The Ge-body cells with Si-based gate dielectrics have slightly higher source-side and drain-side injection than their Si-body counterparts based on their intrinsic dielectric barriers and impact ionization rates. The Ge-based gate dielectric has a key function in tailoring the transverse dielectric barriers for hot-electron injection, while the Schottky barrier source/drain plays a major role in controlling the lateral channel band bending of high-field spots for efficient source-side injection. Incorporating the Ge-based gate dielectrics and Schottky barrier source/drain into the Ge-body, the Ge-based charge-trapping cell can be separately optimized in terms of the lateral channel and the transverse dielectrics to ensure the most efficient low-voltage injection, serving as a promising green cell.
References
[1]
International Roadmap for Device and System (IRDS), 2020 edition
[2]
Welser, J., Pitera, J.W., Goldberg, C.: Future computing hardware for AI. In: IEDM Tech Dig., p. 26 (2018)
[3]
Ishimaru, K.: Future of non-volatile memory -from storage to computing-. In: IEDM Tech Dig., p. 11 (2019)
[4]
Matsubara K, Nagasawa T, Kaneda Y, Mitani H, Iwase T, Aoki Y, Hashimoto K, Morioka T, Maekawa K, Ito T, Kondo H, and Kono T A 2T-MONOS embedded Flash macro with 65-nm SOTB technology achieving 0.15-pJ/bit read energy with 80-MHz access for IoT applications IEEE Solid-State Circuits Lett. 2020 3 58-61
[5]
Takagi S, Noguchi M, Kim M, Kim S-H, Chang C-Y, Yokoyama M, Nishi K, Zhang R, Ke M, and Takenaka M III-V/Ge MOS device technologies for low power integrated systems Solid-State Electron. 2016 125 82-102
[6]
Xue, C.-X., Chang, M.F.: Challenges in circuit designs of nonvolatile-memory based computing-in-memory for AI edge devices. In: Proc. International SoC Design Conference, pp.164–165 (2019)
[7]
Nii, K., Taniguchi, Y., Okuyama, K.: A cost-effective embedded nonvolatile memory with scalable LEE Flash®-G2 SONOS for secure IoT and computing-in-memory (CiM) applications. In: Proc. International Symposium on VLSI Design, Automation and Test, pp. 1–4 (2020)
[8]
Kamata Y High-k/Ge MOSFETs for future nanoelectronics Materialstoday 2008 11 30-38
[9]
Sze SM The Physics of Semiconductor Devices 1981 2 New York Willey
[10]
Goley PS and Hudait MK Germanium based field-effect transistors: challenges and opportunities Materials 2014 7 3 2301-2339
[11]
Kuhn KJ Considerations for ultimate CMOS scaling IEEE Trans. Electron Devices 2012 59 7 1813-1828
[12]
Chou Y-C, Tsai C-W, Yi C-Y, Chung W-H, Wang S-Y, and Chien C-H Used for neuro-inspired-in-memory computing using charge-trapping memtransistor on Germanium as synaptic device IEEE Trans. Electron Devics 2020 67 3605-3609
[13]
Lee J, Park B-G, and Kim Y Implementation of Boolean logic functions in charge trap Flash for in-memory computing IEEE Electron Device Lett. 2019 40 1358-1361
[14]
Fang H-K, Chang-Liao K-S, Chou K-C, Chao T-C, Tsai J-E, Li Y-L, Huang W-H, Shen C-H, and Shieh J-M Impacts of electrical field in tunneling layer on operation characteristics of Poly-Ge charge-trapping Flash memory device IEEE Electron Device Lett. 2020 36 1314-1317
[15]
Huang W-H, Shieh J-M, Shen C-H, Huang T-E, Wang H-H, Yang C-C, Hsieh T-Y, Hsieh J-L, and Yeh W-K Junction-less poly-Ge FinFET and charge-trap NVM fabricated by laser-enabled low thermal budget processes Appl. Phys. Lett. 2016 108
[16]
Ye Z-H, Chang-Liao K-S, Liu L-J, Cheng J-W, and Fang H-K Enhanced programming and erasing speeds of charge-trapping Flash memory device with Ge channel IEEE Electron Device Lett. 2015 36 1314-1317
[17]
Eitan B, Pavan P, Bloom I, Aloni E, Frommer A, and Finzi D NROM: A novel localized trapping, 2-bit nonvolatile memory cell IEEE Electron Device Lett. 2000 21 11 543-545
[18]
Datta A, Bharath Kumar P, and Mahapatra S Dual-Bit/Cell SONOS Flash EEPROMs: impact of channel engineering on programming speed and bit coupling effect IEEE Electron Device Lett. 2007 28 446-448
[19]
Shih C-H and Liang J-T Nonvolatile Schottky barrier multibit cell with source-side injected programming and reverse drain-side hole erasing IEEE Trans. Electron Devices 2010 57 8 1774-1780
[20]
Uchida K, Matsuzawa K, Koga J, Takagi S, and Toriumi A Enhancement of hot-electron generation rate in Schottky source metal-oxide-semiconductor field-effect transistors Appl. Phys. Lett. 2000 76 26 3992-3994
[21]
Shih C-H, Chang W, Wu W-F, and Lien C Multi-level Schottky barrier nanowire SONOS memory with ambipolar N- and P-channel cells IEEE Trans. Electron Devices 2012 59 1614-1620
[22]
Shih C-H and Luo Y-X Effects of dopant-segregated profiles on Schottky barrier charge-trapping Flash memories IEEE Trans. Electron Devices 2014 61 1361-1368
[23]
Luo Y-X and Shih C-H Coupling of carriers injection and charges distribution in Schottky barrier charge-trapping memories using source-side electrons programming Semicond. Sci. Technol. 2014 29
[24]
Teng H-J, Chen Y-H, Tsai J, Chien ND, Lien C, and Shih C-H Transverse scaling of Schottky barrier charge-trapping cells for energy-efficient applications Crystals 2020 10 1036
[25]
Broqvist P, Binder JF, and Pasquarello A Band offsets at the Ge/GeO interface through hybrid density functionals Appl. Phys. Lett. 2009 94 14
[26]
Synopsys Taurus MEDICI User’s Manual, Synopsys Inc., CA (2017)
[27]
Mikawa T, Kagawa S, Kaneda T, Toyama Y, and Mikami O Crystal orientation dependence of ionization rates in germanium Appl. Phys. Lett. 1980 37 4 387-389
[28]
Virginia Semiconductor. The general properties of Si, Ge, SiGe, SiO2 and Si3N4 (2002)
[29]
Fleetwood D, Pantolides S, and Schrimpf RD Defects in Microelectronic Materials and Devices 2008 CRC Press
[30]
Lee, C.H., Nishimura, T., Lu, C., Kabuyanagi, S., Toriumi, A.: Dramatic effects of Hydrogen-induced out-diffusion of oxygen from Ge surface on junction leakage as well as electron mobility in n-channel Ge MOSFETs. In IEDM Tech Dig., p. 780 (2014)
[31]
Chan TY, Ko P-K, and Hu C A simple method to characterize substrate current in MOSFET’s IEEE Electron Devices Lett. 1984 5 12 505-507
[32]
Tam S, Ko P-K, and Hu C Lucky-electron model of channel hot electron injection in MOSFET’s IEEE Trans. Electron Devices 1984 31 9 1116-1125
[33]
Hasnat K, Yeap C-F, Jallepalli S, Shih W-K, Hareland SA, Agostinelli VM Jr, Tasch AF Jr, and Maziar CM A pseudo-lucky electron model for simulation of electron gate current in submicron MOSFET’s IEEE Trans. Electron Devices 1996 43 8 1264-1273
[34]
Igura Y, Matsuoka H, and Takeda E New device degradation due to “cold” carriers created by band-to-band tunneling IEEE Electron Devices Lett. 1989 10 5 227-229
[35]
Sze SM and Gibbons GI Avalanche breakdown voltages of abrupt and linearly graded p-n junctions IN Ge, Si, GaAs, and GaP Appl. Phys. Lett. 1966 8 5 111-113
[36]
Selberherr S Analysis and Simulation of Semiconductor Devices 1984 Springer
[37]
Shih C-H and Yeh S-P Device considerations and design optimizations of dopant segregated Schottky barrier MOSFETs Semicond. Sci. Technol. 2008 23
[38]
Matsuzawa K, Uchida K, and Nishiyama A A unified simulation of Schottky and ohmic contacts IEEE Trans. Electron Devices 2000 47 1 103-108
[39]
Ieong, M., Solomon, P.M., Laux, S.E., Wong, H.S.P., Chidambarrao, D.: Comparison of raised and Schottky source/drain MOSFETs using a novel tunneling contact model. In: IEDM Tech. Dig., pp. 733–736 (1998)
[40]
Andrews JM and Lepselter MP Reverse current-voltage characteristics of metal-silicide Schottky diodes Solid State Electron 1970 13 7 1011-1023
[41]
Xiong S, King TJ, and Bokor J A comparison study of symmetric ultrathin-body double-gate devices with metal source/drain and doped source/drain IEEE Trans. Electron Devices 2005 52 8 1859-1867
Index Terms
- Transverse dielectric and lateral channel band engineering of drain-side and source-side injection in Ge-based charge-trapping memory cells for energy-efficient applications
Index terms have been assigned to the content through auto-classification.
Recommendations
Underlap channel metal source/drain SOI MOSFET for thermally efficient low-power mixed-signal circuits
In this paper it has been shown that employing an underlap channel created by varying the lateral doping straggle in dopant-segregated Schottky barrier SOI MOSFET not only improves the scalability but also suppresses the self-heating effect of this ...
Self-aligned inversion-channel n-InGaAs, p-GaSb, and p-Ge MOSFETs with a common high κ gate dielectric using a CMOS compatible process
Display Omitted Demonstration of using Al2O3/Y2O3 as common gate stacks on InGaAs, GaSb and Ge.Record high device performance of Al2O3/Y2O3 on GaSb for p-MOSFETs.Drain current of 1.5mA/µm and transconductance of 770µS/µm on InGaAs for 1µm gate length n-...
Superior reliability of high mobility (Si)Ge channel pMOSFETs
(Si)Ge channel pMOS technology offers remarkably reduced Negative Bias Temperature Instability (NBTI) at ultra-thin EOT.We ascribe this property to a reduced interaction of channel holes with dielectric defects thanks to energy decoupling.The reduced ...
Comments
Information & Contributors
Information
Published In
© The Author(s), under exclusive licence to Springer Science+Business Media, LLC, part of Springer Nature 2023. Springer Nature or its licensor (e.g. a society or other partner) holds exclusive rights to this article under a publishing agreement with the author(s) or other rightsholder(s); author self-archiving of the accepted manuscript version of this article is solely governed by the terms of such publishing agreement and applicable law.
Publisher
Springer-Verlag
Berlin, Heidelberg
Publication History
Published: 01 February 2023
Accepted: 06 December 2022
Received: 23 February 2022
Author Tags
Qualifiers
- Research-article
Contributors
Other Metrics
Bibliometrics & Citations
Bibliometrics
Article Metrics
- 0Total Citations
- 0Total Downloads
- Downloads (Last 12 months)0
- Downloads (Last 6 weeks)0
Reflects downloads up to 30 Dec 2024