Article

ACTL ∩ LTL synthesis

Author:

Rüdiger EhlersAuthors Info & Claims

CAV'12: Proceedings of the 24th international conference on Computer Aided Verification

Pages 39 - 54

https://doi.org/10.1007/978-3-642-31424-7_9

Published: 07 July 2012 Publication History

Abstract

We study the synthesis problem for specifications of the common fragment of ACTL (computation tree logic with only universal path quantification) and LTL (linear-time temporal logic). Key to this setting is a novel construction for translating properties from LTL to very-weak automata, whenever possible. Such automata are structurally simple and thus amenable to optimizations as well as symbolic implementations.

Based on this novel construction, we describe a synthesis approach that inherits the efficiency of generalized reactivity(1) synthesis [27], but is significantly richer in terms of expressivity.

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Cited By

Shimakawa MUeno AMochizuki STomita THagihara SYonezaki N(2019)Towards Efficient Implementation of Realizability Checking for Reactive System SpecificationsProceedings of the 2019 8th International Conference on Software and Computer Applications10.1145/3316615.3316634(347-352)Online publication date: 19-Feb-2019
https://dl.acm.org/doi/10.1145/3316615.3316634
Boker UShaulian Y(2018)Automaton-Based Criteria for Membership in CTLProceedings of the 33rd Annual ACM/IEEE Symposium on Logic in Computer Science10.1145/3209108.3209143(155-164)Online publication date: 9-Jul-2018
https://dl.acm.org/doi/10.1145/3209108.3209143

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Evaluation of SAT-based Bounded Model Checking of ACTL Properties
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Bounded model checking (BMC) based on SAT has been introduced as a complementary method to BDDbased symbolic model checking of LTL and ACTL properties in recent years. For general LTL and ACTL properties, BMC has traditionally aimed mainly at error ...
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Abstract
Reactive synthesis holds the promise of generating automatically a verifiably correct program from a high-level specification. A popular such specification language is Linear Temporal Logic (LTL). Unfortunately, synthesizing programs from general ...

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Published In

cover image Guide Proceedings

CAV'12: Proceedings of the 24th international conference on Computer Aided Verification

July 2012

789 pages

ISBN:9783642314230

Editors:
P. Madhusudan
Dept. of Computer Science, University of Illinois at Urbana-Champaign, Urbana, IL
,
Sanjit A. Seshia
Dept. of Electrical Engineering and Computer Science, University of California, Berkeley, Berkeley, CA

Sponsors

NEC Labs: NEC Labs
IBMR: IBM Research
Intel: Intel
Microsoft Research: Microsoft Research

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Springer-Verlag

Berlin, Heidelberg

Publication History

Published: 07 July 2012

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Cited By

Shimakawa MUeno AMochizuki STomita THagihara SYonezaki N(2019)Towards Efficient Implementation of Realizability Checking for Reactive System SpecificationsProceedings of the 2019 8th International Conference on Software and Computer Applications10.1145/3316615.3316634(347-352)Online publication date: 19-Feb-2019
https://dl.acm.org/doi/10.1145/3316615.3316634
Boker UShaulian Y(2018)Automaton-Based Criteria for Membership in CTLProceedings of the 33rd Annual ACM/IEEE Symposium on Logic in Computer Science10.1145/3209108.3209143(155-164)Online publication date: 9-Jul-2018
https://dl.acm.org/doi/10.1145/3209108.3209143

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