Design principles for synthesizable processor cores
Pages 111 - 122
Abstract
As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput on FPGA-based processor cores: first, superpipelining enables higher-frequency system clocks, and second, predicated instructions circumvent costly pipeline stalls due to branches. To evaluate their effects, we develop Tinuso, a processor architecture optimized for FPGA implementation. We demonstrate through the use of micro-benchmarks that our principles guide the design of a processor core that improves performance by an average of 38% over a similar Xilinx MicroBlaze configuration.
References
[1]
Ahuja, P., Clark, D., Rogers, A.: The performance impact of incomplete bypassing in processor pipelines. In: Proceedings of International Symposium on Microarchitecture MICRO - 28 (1995)
[2]
ARM: ARM Cortex-M1 Frequency and Area, http://www.arm.com/products/processors/cortex-m/cortex-m1.php (retrieved on October 5, 2011)
[3]
Bird, S., Phansalkar, A., John, L., Mercas, A., Idukuru, R.: Performance characterization of SPEC CPU benchmarks on Intel's Core microarchitecture based processor. In: Proceedings of SPEC Benchmark Workshop (2007)
[4]
Connors, D. A., Puiatti, J.-M., August, D. I., Crozier, K. M., Hwu, W.-m. W.: An architecture framework for introducing predicated execution into embedded microprocessors. In: Amestoy, P. R., Berger, P., Daydé, M., Duff, I. S., Frayssé, V., Giraud, L., Ruiz, D. (eds.) Euro-Par 1999. LNCS, vol. 1685, p. 1301. Springer, Heidelberg (1999)
[5]
Ehliar, A., Karlstrom, P., Liu, D.: A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA. In: Proceedings of International Conference on Field Programmable Logic and Applications, FPL-18 (2008)
[6]
Ehliar, A., Liu, D.: An ASIC perspective on fpga optimizations. In: Proceedings of International Conference on Field Programmable Logic and Applications, FPL-20 (2009)
[7]
Mesa-Martinez, F., et al.: SCOORE santa cruz out-of-order RISC engine, FPGA design issues. In: Proceedings of Workshop on Architectural Research Prototyping WARP, Held in Conjunction with ISCA-33 (2006)
[8]
Lattice Semiconductor: Latticemico32 processor reference manual v8.1 (2010), http://www.latticesemi.com/documents/lm32_archman.pdf (retrieved on March 25, 2011)
[9]
Lattice Semiconductor: LatticeMico32 Product Brief I0186 (2011), http://www.latticesemi.com/documents/I0186.pdf (retrieved on October 5, 2011)
[10]
Palacharla, S., Jouppi, N., Smith, J.: Complexity-effective superscalar processors. In: Proceedings of International Symposium on Computer Architecture, ISCA - 24 (1997)
[11]
Tong, J., Anderson, I., Khalid, M.: Soft-core processors for embedded systems. In: Proceedings of International Conference on Microelectronics, ICM-18 (2006)
[12]
Xilinx: MicroBlaze Processor Reference Guide UG081 v12.0 (2011), http://www.xilinx.com/support/documentation/ sw manuals/xilinx13_1/mb_ref_guide.pdf (retrieved on October 5, 2011)
- Design principles for synthesizable processor cores
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Sponsors
- German Comp Soc: GI - Gesellshaft for Informatik
- IEEE
- Xilinx: Xilinx Inc.
- VDE: Assoc for German Electrical Engineers
- IFIP: International Federation for Information Processing
Publisher
Springer-Verlag
Berlin, Heidelberg
Publication History
Published: 28 February 2012
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