About MasterT

MasterT · 2023-11-08

ADC analog bandwidth tests:--board nucleo-G474re, on-board voltage reference.--sampling rate 2.8 msps, free-run mode, 12-bits, --156 kHz & 19.47 MHz. Approximately at 19 MHz ADC has ENOB < 6 bits, limiting factor seems to be aperture jitter about 12...

MasterT · 2019-12-15

CubeMx version 5.4.0., STM32Cube_FW_H7_V1.5.0ADC Oversampling Ratio EditBox doesn't allow to enter 1024, max value 1023. But it should, HAL_ driver makes subtraction -1, so 1024 is correct value.

MasterT · 2019-12-05

I discovered that Ethernet module on the nucleo-H743zi generates a lot of interference for analog domain. I thought, that if peripheral devise was not configured in the software and was not given explicit permition to run, it should stay in power do...

MasterT · 2019-12-03

Seems there is an error in the STLink firmware (upgraded to the latest version just now), clock is off about 1%.

MasterT · 2019-05-11

I have two nucleo-144 boards, stm32F767zi and stm32H743zi. Both cortex-M7, pin compatible, and pretty close in AHBx (GPIO) clock, 216 vs 200 MHz.Testing TFT LCD display library, that required fast 8-bits access to the LCD data bus, I discovered that ...

MasterT · 2024-11-02

>> "A switching regulator will have massive problems here because a positive and a negative voltage are required. "There are switching power supplies on a market that provide both: positive and negative voltages .With all due respect, all post is jus...

MasterT · 2024-11-01

22k & 0.56uF -> 12.9 Hz cut-off frequency -3dB.Other question is acoustic system to reproduce anything below 20Hz.

MasterT · 2024-11-01

Those enormous capacitors likely suggested based on assumption of simplest power supply in use (transformer + diodes bridge rectifier) and also 4 Ohm load. For switching power supply big cap's are not required. Since <20 Hz imply not audio, than more...

MasterT · 2024-10-24

Elaborate on specific of limit, is it linear or something like trip /switching off quickly?I'd start from research on DC/DC switching regulators, most of them (if not all) employ current limiting OCP circuitry, just find one in desired voltage rang...

MasterT · 2024-10-24

The parameter you are hunting is called PLL / VCO jitter. Look in the data sheet, and on-line. Higher multiplier degrades specification, since VCO is running for longer period of time and drift away w/o syncing.Jitter is more important for analog dom...

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stm32G474re adc performance

stm32CubeMX stm32h743 ADC oversampling settings

High noise level in the analog domain on nucleo-H743zi

ST-LINK provides 8.08 MHz instead of 8.000 on new nucleo-H743ZI2.

Why stm32H743zi has longer access time to GPIO interface?

Re: TDA7294 Bridge application

Re: TDA7294 Bridge application

Re: TDA7294 Bridge application

Re: Limiting DC current@110V to 2A

Re: The question of setting clock multipliers and dividers