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Sequential Circuits-ppt_2.pdf

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1. The document discusses sequential circuits and various types of latches and flip-flops used in sequential logic, including SR latches, D latches, edge-triggered flip-flops, JK flip-flops and T flip-flops. 2. It describes how to analyze sequential circuits using state tables, state equations, state diagrams and flip-flop input equations. 3. As an example, it shows the analysis of a 2-bit up counter sequential circuit using D flip-flops, including deriving the next state equations and constructing the state table and state diagram.

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Electronics & Communication Engineering  Digital Electronics –II Ravinder Kumar Govt. Polytechnic, Manesar 1
2 Chapter-5, Sequential Circuits Synchronous Sequential Logic Every digital system is likely to have combinational circuits, most systems encountered in practice also include storage elements, which require that the system be described in term of sequential logic.
3 Synchronous Clocked Sequential Circuit A sequential circuit may use many flip-flops to store as many bits as necessary. The outputs can come either from the combinational circuit or from the flip-flops or both.
4 5-2 Latches SR Latch The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates. It has two inputs labeled S for set and R for reset.
5 SR Latch with NAND Gates
6 SR Latch with Control Input The operation of the basic SR latch can be modified by providing an additional control input that determines when the state of the latch can be changed. In Fig. 5-5, it consists of the basic SR latch and two additional NAND gates.
7 D Latch One way to eliminate the undesirable condition of the indeterminate state in SR latch is to ensure that inputs S and R are never equal to 1 at the same time in Fig 5-5. This is done in the D latch.
8 Graphic Symbols for latches A latch is designated by a rectangular block with inputs on the left and outputs on the right. One output designates the normal output, and the other designates the complement output.
9 5-3 Flip-Flops The state of a latch or flip-flop is switched by a change in the control input. This momentary change is called a trigger and the transition it cause is said to trigger the flip-flop. The D latch with pulses in its control input is essentially a flip-flop that is triggered every time the pulse goes to the logic 1 level. As long as the pulse input remains in the level, any changes in the data input will change the output and the state of the latch.
10 Clock Response in Latch In Fig (a) a positive level response in the control input allows changes, in the output when the D input changes while the clock pulse stays at logic 1.
11 Clock Response in Flip-Flop
12 Edge-Triggered D Flip-Flop The first latch is called the master and the second the slave. The circuit samples the D input and changes its output Q only at the negative-edge of the controlling clock. CLK D 1 1 0 0 1 1 … Y 1 1 0 0 1 1 … Q ? 1 1 0 0 1 ….
13 D-Type Positive-Edge-Triggered Flip-Flop Another more efficient construction of an edge-triggered D flip-flop uses three SR latches. Two latches respond to the external D(data) and CLK(clock) inputs. The third latch provides the outputs for the flip-flop. Ref. p.175 texts
14 Graphic Symbol for Edge-Triggered D Flip-Flop
15 Other Flip-Flops JK Flip-Flop There are three operations that can be performed with a flip-flop: set it to 1, reset it to 0, or complement its output. The JK flip-flop performs all three operations. The circuit diagram of a JK flip-flop constructed with a D flip-flop and gates.
16 JK Flip-Flop The J input sets the flip-flop to 1, the K input resets it to 0, and when both inputs are enabled, the output is complemented. This can be verified by investigating the circuit applied to the D input: D = J Q` + K` Q
17 T Flip-Flop The T(toggle) flip-flop is a complementing flip-flop and can be obtained from a JK flip-flop when inputs J and K are tied together.
18 T Flip-Flop The T flip-flop can be constructed with a D flip-flop and an exclusive-OR gates as shown in Fig. (b). The expression for the D input is D = T Q = TQ` + T`Q
19 Characteristic Equations D flip-flop Characteristic Equations Q(t + 1) = D JK flip-flop Characteristic Equations T flip-flop Characteristic Equations Q(t + 1) = JQ` + K`Q Q(t + 1) = T Q = TQ` + T`Q
20 Direct Inputs Some flip-flops have asynchronous inputs that are used to force the flip-flop to a particular state independent of the clock. The input that sets the flip-flop to 1 is called present or direct set. The input that clears the flip-flop to 0 is called clear or direct reset. When power is turned on a digital system, the state of the flip-flops is unknown. The direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation.
21 D Flip-Flop with Asynchronous Reset A positive-edge-triggered D flip-flop with asynchronous reset is shown in Fig(a).
22 D Flip-Flop with Asynchronous Reset
23 5-4 Analysis of Clocked Sequential Circuits The analysis of a sequential circuit consists of obtaining a table or a diagram for the time sequence of inputs, outputs, and internal states. It is also possible to write Boolean expressions that describe the behavior of the sequential circuit. These expressions must include the necessary time sequence, either directly or indirectly.
24 State Equations The behavior of a clocked sequential circuit can be described algebraically by means of state equations. A state equation specifies the next state as a function of the present state and inputs. Consider the sequential circuit shown in Fig. 5-15. It consists of two D flip-flops A and B, an input x and an output y.
25 Fig.5-15 Example of Sequential Circuit
26 State Equation A(t+1) = A(t) x(t) + B(t) x(t) B(t+1) = A`(t) x(t) A state equation is an algebraic expression that specifies the condition for a flip-flop state transition. The left side of the equation with (t+1) denotes the next state of the flip- flop one clock edge later. The right side of the equation is Boolean expression that specifies the present state and input conditions that make the next state equal to 1. Y(t) = (A(t) + B(t)) x(t)`
27 State Table The time sequence of inputs, outputs, and flip-flop states can be enumerated in a state table (sometimes called transition table).
28 State Diagram The information available in a state table can be represented graphically in the form of a state diagram. In this type of diagram, a state is represented by a circle, and the transitions between states are indicated by directed lines connecting the circles. 1/0 : means input =1 output=0
29 Flip-Flop Input Equations The part of the combinational circuit that generates external outputs is descirbed algebraically by a set of Boolean functions called output equations. The part of the circuit that generates the inputs to flip-flops is described algebraically by a set of Boolean functions called flip-flop input equations. The sequential circuit of Fig. 5-15 consists of two D flip-flops A and B, an input x, and an output y. The logic diagram of the circuit can be expressed algebraically with two flip-flop input equations and an output equation: DA = Ax + Bx DB = A`x y = (A + B)x`
30 Analysis with D Flip-Flop The circuit we want to analyze is described by the input equation DA = A x y The DA symbol implies a D flip-flop with output A. The x and y variables are the inputs to the circuit. No output equations are given, so the output is implied to come from the output of the flip-flop.
31 Analysis with D Flip-Flop The binary numbers under Axy are listed from 000 through 111 as shown in Fig. 5-17(b). The next state values are obtained from the state equation A(t+1) = A x y The state diagram consists of two circles-one for each state as shown in Fig. 5-17(c)
32 Analysis with JK Flip-Flops
33 Analysis with JK Flip-Flop The circuit can be specified by the flip-flop input equations JA = B KA = Bx` JB = x` KB = A`x + Ax` = A x
34 Analysis with JK Flip-Flops A(t + 1) = JA` + K`A B(t + 1) = JB` + K`B Substituting the values of JA and KA from the input equations, we obtain the state equation for A: A(t + 1) = BA` + (Bx`)`A = A`B + AB` +Ax The state equation provides the bit values for the column under next state of A in the state table. Similarly, the state equation for flip-flop B can be derived from the characteristic equation by substituting the values of JB and KB: B(t + 1) = x`B` + (A x)`B = B`x` + ABx + A`Bx`
35 Analysis with JK Flip-Flops The state diagram of the sequential circuit is shown in Fig. 5-19.
36 Analysis With T Flip-Flops Characteristic equation Q(t + 1) = T Q = T`Q + TQ` 00/0 : means state is 00 output is 0
37 Analysis With T Flip-Flops Consider the sequential circuit shown in Fig. 5-20. It has two flip-flops A and B, one input x, and one output y. It can be described algebraically by two input equations and an output equation: TA = Bx TB = x y = AB A(t+1)=(Bx)’A+(Bx)A’ =AB’+Ax’+A’Bx B(t+1)=xB Use present state as inputs
38 Mealy and Moore Models (1) • The most general model of a sequential circuit has inputs, outputs, and internal states. It is customary to distinguish between two models of sequential circuits: the Mealy model and the Moore model • They differ in the way the output is generated. - In the Mealy model, the output is a function of both the present state and input. - In the Moore model, the output is a function of the present state only.
39 Mealy and Moore Models (2) When dealing with the two models, some books and other technical sources refer to a sequential circuit as a finite state machine abbreviated FSM. - The Mealy model of a sequential circuit is referred to as a Mealy FSM or Mealy machine. - The Moore model is refereed to as a Moore FSM or Moore machine.
40 Sequential Circuit Analysis  Design of a simple sequential circuit  Analysis of an existing circuit
State machine synthesis  Creation of state machine  State machines are digital sequential circuits that transition through a series of states according to their design.  For the creation of any such circuit always start with the problem definition or the circuit specification. 41
Problem Statement  Design a 2 bit up counter that has no preset state and continually cycles thought the 4 states.  This can be defined by a table – called a state table.  Present State Next State  00 01  01 10  10 11  11 00 42
A diagram representation  This form is termed a state diagram 43
Sequential circuits  Basic form and elements 44
This problem  Storage Elements – 2 Flip-flops  No inputs  Current state is the output  Combination logic generate the next state value. 45
Generating Next State  Use K maps generated from State Table 46
The Circuit  Using D FF 47
Sequential Circuit analysis  The circuit to analyze  How to start?  How about with the next state equations? 48
Next State Equations  For DA have an AND-OR set of gates to generate the input.  The upper AND gate has inputs X and A  The lower AND gate has inputs X and B  So DA = AX + BX  For DB have a single AND gate whose inputs are X and A’  So DB = A’X 49
Also have an output Y  The OR gate has inputs A and B  This feeds into a 2-input AND gate whose other input is X’  Thus Y = (A+B)X’  Now having these equations can construct the state table for the state machine 50
The state table  For generation of the next state you have the Present State as indicated by A and B plus the input X. This next state becomes the current state on the clock. 51
Another form of the state table  Two-dimensional form of the same table 52
 The state diagram for this systems is  Not the notation on the diagram  On transition arcs – input/output The state Diagram 53

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Sequential Circuits-ppt_2.pdf

  • 1. Electronics & Communication Engineering  Digital Electronics –II Ravinder Kumar Govt. Polytechnic, Manesar 1
  • 2. 2 Chapter-5, Sequential Circuits Synchronous Sequential Logic Every digital system is likely to have combinational circuits, most systems encountered in practice also include storage elements, which require that the system be described in term of sequential logic.
  • 3. 3 Synchronous Clocked Sequential Circuit A sequential circuit may use many flip-flops to store as many bits as necessary. The outputs can come either from the combinational circuit or from the flip-flops or both.
  • 4. 4 5-2 Latches SR Latch The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates. It has two inputs labeled S for set and R for reset.
  • 5. 5 SR Latch with NAND Gates
  • 6. 6 SR Latch with Control Input The operation of the basic SR latch can be modified by providing an additional control input that determines when the state of the latch can be changed. In Fig. 5-5, it consists of the basic SR latch and two additional NAND gates.
  • 7. 7 D Latch One way to eliminate the undesirable condition of the indeterminate state in SR latch is to ensure that inputs S and R are never equal to 1 at the same time in Fig 5-5. This is done in the D latch.
  • 8. 8 Graphic Symbols for latches A latch is designated by a rectangular block with inputs on the left and outputs on the right. One output designates the normal output, and the other designates the complement output.
  • 9. 9 5-3 Flip-Flops The state of a latch or flip-flop is switched by a change in the control input. This momentary change is called a trigger and the transition it cause is said to trigger the flip-flop. The D latch with pulses in its control input is essentially a flip-flop that is triggered every time the pulse goes to the logic 1 level. As long as the pulse input remains in the level, any changes in the data input will change the output and the state of the latch.
  • 10. 10 Clock Response in Latch In Fig (a) a positive level response in the control input allows changes, in the output when the D input changes while the clock pulse stays at logic 1.
  • 11. 11 Clock Response in Flip-Flop
  • 12. 12 Edge-Triggered D Flip-Flop The first latch is called the master and the second the slave. The circuit samples the D input and changes its output Q only at the negative-edge of the controlling clock. CLK D 1 1 0 0 1 1 … Y 1 1 0 0 1 1 … Q ? 1 1 0 0 1 ….
  • 13. 13 D-Type Positive-Edge-Triggered Flip-Flop Another more efficient construction of an edge-triggered D flip-flop uses three SR latches. Two latches respond to the external D(data) and CLK(clock) inputs. The third latch provides the outputs for the flip-flop. Ref. p.175 texts
  • 14. 14 Graphic Symbol for Edge-Triggered D Flip-Flop
  • 15. 15 Other Flip-Flops JK Flip-Flop There are three operations that can be performed with a flip-flop: set it to 1, reset it to 0, or complement its output. The JK flip-flop performs all three operations. The circuit diagram of a JK flip-flop constructed with a D flip-flop and gates.
  • 16. 16 JK Flip-Flop The J input sets the flip-flop to 1, the K input resets it to 0, and when both inputs are enabled, the output is complemented. This can be verified by investigating the circuit applied to the D input: D = J Q` + K` Q
  • 17. 17 T Flip-Flop The T(toggle) flip-flop is a complementing flip-flop and can be obtained from a JK flip-flop when inputs J and K are tied together.
  • 18. 18 T Flip-Flop The T flip-flop can be constructed with a D flip-flop and an exclusive-OR gates as shown in Fig. (b). The expression for the D input is D = T Q = TQ` + T`Q
  • 19. 19 Characteristic Equations D flip-flop Characteristic Equations Q(t + 1) = D JK flip-flop Characteristic Equations T flip-flop Characteristic Equations Q(t + 1) = JQ` + K`Q Q(t + 1) = T Q = TQ` + T`Q
  • 20. 20 Direct Inputs Some flip-flops have asynchronous inputs that are used to force the flip-flop to a particular state independent of the clock. The input that sets the flip-flop to 1 is called present or direct set. The input that clears the flip-flop to 0 is called clear or direct reset. When power is turned on a digital system, the state of the flip-flops is unknown. The direct inputs are useful for bringing all flip-flops in the system to a known starting state prior to the clocked operation.
  • 21. 21 D Flip-Flop with Asynchronous Reset A positive-edge-triggered D flip-flop with asynchronous reset is shown in Fig(a).
  • 22. 22 D Flip-Flop with Asynchronous Reset
  • 23. 23 5-4 Analysis of Clocked Sequential Circuits The analysis of a sequential circuit consists of obtaining a table or a diagram for the time sequence of inputs, outputs, and internal states. It is also possible to write Boolean expressions that describe the behavior of the sequential circuit. These expressions must include the necessary time sequence, either directly or indirectly.
  • 24. 24 State Equations The behavior of a clocked sequential circuit can be described algebraically by means of state equations. A state equation specifies the next state as a function of the present state and inputs. Consider the sequential circuit shown in Fig. 5-15. It consists of two D flip-flops A and B, an input x and an output y.
  • 25. 25 Fig.5-15 Example of Sequential Circuit
  • 26. 26 State Equation A(t+1) = A(t) x(t) + B(t) x(t) B(t+1) = A`(t) x(t) A state equation is an algebraic expression that specifies the condition for a flip-flop state transition. The left side of the equation with (t+1) denotes the next state of the flip- flop one clock edge later. The right side of the equation is Boolean expression that specifies the present state and input conditions that make the next state equal to 1. Y(t) = (A(t) + B(t)) x(t)`
  • 27. 27 State Table The time sequence of inputs, outputs, and flip-flop states can be enumerated in a state table (sometimes called transition table).
  • 28. 28 State Diagram The information available in a state table can be represented graphically in the form of a state diagram. In this type of diagram, a state is represented by a circle, and the transitions between states are indicated by directed lines connecting the circles. 1/0 : means input =1 output=0
  • 29. 29 Flip-Flop Input Equations The part of the combinational circuit that generates external outputs is descirbed algebraically by a set of Boolean functions called output equations. The part of the circuit that generates the inputs to flip-flops is described algebraically by a set of Boolean functions called flip-flop input equations. The sequential circuit of Fig. 5-15 consists of two D flip-flops A and B, an input x, and an output y. The logic diagram of the circuit can be expressed algebraically with two flip-flop input equations and an output equation: DA = Ax + Bx DB = A`x y = (A + B)x`
  • 30. 30 Analysis with D Flip-Flop The circuit we want to analyze is described by the input equation DA = A x y The DA symbol implies a D flip-flop with output A. The x and y variables are the inputs to the circuit. No output equations are given, so the output is implied to come from the output of the flip-flop.
  • 31. 31 Analysis with D Flip-Flop The binary numbers under Axy are listed from 000 through 111 as shown in Fig. 5-17(b). The next state values are obtained from the state equation A(t+1) = A x y The state diagram consists of two circles-one for each state as shown in Fig. 5-17(c)
  • 32. 32 Analysis with JK Flip-Flops
  • 33. 33 Analysis with JK Flip-Flop The circuit can be specified by the flip-flop input equations JA = B KA = Bx` JB = x` KB = A`x + Ax` = A x
  • 34. 34 Analysis with JK Flip-Flops A(t + 1) = JA` + K`A B(t + 1) = JB` + K`B Substituting the values of JA and KA from the input equations, we obtain the state equation for A: A(t + 1) = BA` + (Bx`)`A = A`B + AB` +Ax The state equation provides the bit values for the column under next state of A in the state table. Similarly, the state equation for flip-flop B can be derived from the characteristic equation by substituting the values of JB and KB: B(t + 1) = x`B` + (A x)`B = B`x` + ABx + A`Bx`
  • 35. 35 Analysis with JK Flip-Flops The state diagram of the sequential circuit is shown in Fig. 5-19.
  • 36. 36 Analysis With T Flip-Flops Characteristic equation Q(t + 1) = T Q = T`Q + TQ` 00/0 : means state is 00 output is 0
  • 37. 37 Analysis With T Flip-Flops Consider the sequential circuit shown in Fig. 5-20. It has two flip-flops A and B, one input x, and one output y. It can be described algebraically by two input equations and an output equation: TA = Bx TB = x y = AB A(t+1)=(Bx)’A+(Bx)A’ =AB’+Ax’+A’Bx B(t+1)=xB Use present state as inputs
  • 38. 38 Mealy and Moore Models (1) • The most general model of a sequential circuit has inputs, outputs, and internal states. It is customary to distinguish between two models of sequential circuits: the Mealy model and the Moore model • They differ in the way the output is generated. - In the Mealy model, the output is a function of both the present state and input. - In the Moore model, the output is a function of the present state only.
  • 39. 39 Mealy and Moore Models (2) When dealing with the two models, some books and other technical sources refer to a sequential circuit as a finite state machine abbreviated FSM. - The Mealy model of a sequential circuit is referred to as a Mealy FSM or Mealy machine. - The Moore model is refereed to as a Moore FSM or Moore machine.
  • 40. 40 Sequential Circuit Analysis  Design of a simple sequential circuit  Analysis of an existing circuit
  • 41. State machine synthesis  Creation of state machine  State machines are digital sequential circuits that transition through a series of states according to their design.  For the creation of any such circuit always start with the problem definition or the circuit specification. 41
  • 42. Problem Statement  Design a 2 bit up counter that has no preset state and continually cycles thought the 4 states.  This can be defined by a table – called a state table.  Present State Next State  00 01  01 10  10 11  11 00 42
  • 43. A diagram representation  This form is termed a state diagram 43
  • 44. Sequential circuits  Basic form and elements 44
  • 45. This problem  Storage Elements – 2 Flip-flops  No inputs  Current state is the output  Combination logic generate the next state value. 45
  • 46. Generating Next State  Use K maps generated from State Table 46
  • 48. Sequential Circuit analysis  The circuit to analyze  How to start?  How about with the next state equations? 48
  • 49. Next State Equations  For DA have an AND-OR set of gates to generate the input.  The upper AND gate has inputs X and A  The lower AND gate has inputs X and B  So DA = AX + BX  For DB have a single AND gate whose inputs are X and A’  So DB = A’X 49
  • 50. Also have an output Y  The OR gate has inputs A and B  This feeds into a 2-input AND gate whose other input is X’  Thus Y = (A+B)X’  Now having these equations can construct the state table for the state machine 50
  • 51. The state table  For generation of the next state you have the Present State as indicated by A and B plus the input X. This next state becomes the current state on the clock. 51
  • 52. Another form of the state table  Two-dimensional form of the same table 52
  • 53.  The state diagram for this systems is  Not the notation on the diagram  On transition arcs – input/output The state Diagram 53