A 120-Gbit/s 1.27-W 520-mVpp 2: 1 Multiplexer IC Using Self-Aligned InP/InGaAs/InP DHBTs with Emitter Mesa Passivation

Yutaka ARAYASHIKI; Yukio OHKUBO; Taisuke MATSUMOTO; Yoshiaki AMANO; Akio TAKAGI; Yutaka MATSUOKA

doi:10.1587/transele.E93.C.1273

Special Section on Heterostructure Microelectronics with TWHM 2009

A 120-Gbit/s 1.27-W 520-mVpp 2: 1 Multiplexer IC Using Self-Aligned InP/InGaAs/InP DHBTs with Emitter Mesa Passivation

Yutaka ARAYASHIKI, Yukio OHKUBO, Taisuke MATSUMOTO, Yoshiaki AMANO, Akio TAKAGI, Yutaka MATSUOKA

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Keywords: DHBT, self-aligned, ledge, MUX, broadband impedance matching, module

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2010 Volume E93.C Issue 8 Pages 1273-1278

DOI https://doi.org/10.1587/transele.E93.C.1273

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Abstract

We fabricated a 2: 1 multiplexer IC (MUX) with a retiming function by using 1-µm self-aligned InP/InGaAs/InP double-heterojunction bipolar transistors (DHBTs) with emitter mesa passivation ledges. The MUX operated at 120Gbit/s with a power dissipation of 1.27W and output amplitude of 520mV when measured on the wafer. When assembled in a module using V-connectors, the MUX operated at 113Gbit/s with a 514-mV output amplitude and a power dissipation of 1.4W.

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