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A methodology for the efficient architectural exploration of energy-delay trade-offs for embedded systems

Published: 09 March 2003 Publication History

Abstract

The main goal of this paper is to identify the best architecture of an embedded system by considering at the same time energy and delay, avoiding the comprehensive analysis of the architectural design space. We adopt the Energy-Delay Product (EDP) as the evaluation metric to compare the alternative architectures of the target system. The paper analyzes an extended adaptive random search algorithm (ADGREED) to efficiently explore the architectural design space. The ADGREED algorithm is a pseudo-random optimisation algorithm that combines the best potentialities of the adaptive random search (ADRAS) and the Greedy deterministic algorithm. The analysis has been carried out through the architectural optimisation of the memory sub-system of a real-word embedded system executing the set of Mediabench benchmarks for multimedia applications. The reported experimental results have shown a reduction up to one order of magnitude of the number of design alternatives analyzed during the exploration phase, while maintaining very high accuracy.

References

[1]
N. Vijaykrishnan, M. Kandemir, M. J. Irwin, H. S. Kim, and W. Ye. Energy-driven integrated hardware-software optimizations using simplepower. In ISCA 2000: 2000 International Symposium on Computer Architecture, Vancouver BC, Canada, June 2000.
[2]
Y. Li and J. Henkel. A framework for estimating and minimizing energy dissipation of embedded hw/sw systems. In DAC-35: ACM/IEEE Design Automation Conference, June 1998.
[3]
T. M. Conte, K. N. Menezes, S. W. Sathaye, and M. C. Toburen. System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design. IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 8(2):129--137, Apr. 2000.
[4]
David Brooks, Vivek Tiwari, and Margaret Martonosi. Wattch: a framework for architectural-level power analysis and optimizations. In Proceedings ISCA 2000, pages 83--94, 2000.
[5]
N. Bellas, I. N. Hajj, D. Polychronopoulos, and G. Stamoulis. Architectural and compiler techniques for energy reduction in high-performance microprocessors. IEEE Transactions on Very Large Scale of Integration (VLSI) Systems, 8(3), June 2000.
[6]
Tony D. Givargis, Frank Vahid, and Jörg Henkel. Evaluating power consumption of parameterized cache and bus architectures in system-on-a-chip designs. IEEE Transactions on Very Large Scale of Integration (VLSI) Systems, 9(4), August 2001.
[7]
J. K. Kin, M. Gupta, and W. H. Mangione-Smith. Filtering Memory References to Increase Energy Efficiency. IEEE Trans. on Computers, 49(1), Jan. 2000.
[8]
L. Benini, A. Macii, E. Macii, and M. Poncino. Increasing energy efficiency of embedded systems by application-specific memory hierarchy generation. Design and Test of Computers, 17(2):74--85, April-June 2000.
[9]
R. I. Bahar, G. Albera, and S. Manne. Power and performance tradeoffs using various caching strategies. In ISLPED-98: ACM/IEEE Int. Symposium on Low Power Electronics and Design, Monterey, CA, 1998.
[10]
C. L. Su and A. M. Despain. Cache design trade-offs for power and performance optimization: A case study. In ISLPED-95: ACM/IEEE Int. Symposium on Low Power Electronics and Design, 1995.
[11]
M. B. Kamble and K. Ghose. Analytical energy dissipation models for low power caches. In ISLPED-97: ACM/IEEE Int. Symposium on Low Power Electronics and Design, 1997.
[12]
S. E. Wilton and N. Jouppi. An enhanced access and cycle time model for on-chip caches. Technical Report 93/5, Digital Equipment Corporation Western Research Lab., 1994.
[13]
P. Hicks, M. Walnock, and R. M. Owens. Analysis of power consumption in memory hierarchies. In ISLPED-97: ACM/IEEE Int. Symposium on Low Power Electronics and Design, pages 239--242, Monterey, CA, 1997.
[14]
W.-T. Shiue and C. Chakrabarti. Power estimation of system-level buses for microprocessor-based architectures: A case study. In Proc. DAC99: Design Automation Conference, New Orleans, LU, 1999.
[15]
L. Benini, D. Bruni, M. Chinosi, C. Silvano, V. Zaccaria, and R. Zafalon. A power modeling and estimation framework for vliw-based embedded systems. In Proceedings of International Workshop-Power And Timing Modeling, Optimization and Simulation, PATMOS'01, 26--28 2001.
[16]
Anatoly A. Zhigljavsky. Theory of global random search, volume 65. Kluwer Academic Publishers Group, Dordrecht, 1991.
[17]
P. Faraboschi, G. Brown, J. Fisher, G. Desoli, and F. Homewood. Lx: a technology platform for customizable vliw embedded processing. In Proceedings of the International Symposium on Computer Architecture, pages 203--213, June 2000.
[18]
C. Lee, M. Potkonjak, and W. H. Mangione-Smith. Mediabench: A tool for evaluating multimedia and communication systems. In Proceedings of Micro 30, 1997.
[19]
Andrea Bona, Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria, and Roberto Zafalon. Energy Estimation and Optimization of Embedded VLIW Processors Based on Instruction Clustering. In Proceedings of the 39th Design Automation Conference DAC'02, pages 886--891, June 2002.
[20]
S. Wilton and N. Jouppi. CACTI:An Enhanced Cache Access and Cycle Time Model. IEEE Journal of Solid-State Circuits, 31(5):677--688, 1996.
[21]
Itoh Sasaki Nakagome. Trends in low-power ram circuit technologies. Proceedings of the IEEE, 83(4), April 1995.

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cover image ACM Conferences
SAC '03: Proceedings of the 2003 ACM symposium on Applied computing
March 2003
1268 pages
ISBN:1581136242
DOI:10.1145/952532
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 09 March 2003

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  1. design space exploration
  2. embedded systems

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SAC03: ACM Symposium on Applied Computing
March 9 - 12, 2003
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Overall Acceptance Rate 1,650 of 6,669 submissions, 25%

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