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Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs

Published: 28 April 2003 Publication History

Abstract

The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combine improvements on algorithm and logic level. To reduce the power consumption of dynamic logic, a method for using single-rail structures is presented including a new scheme to realize inverting logic functions. It is shown that such structure is most efficient when redundant number systems are utilized. These self-timed logic is integrated in a global clock system using the Asynchronous Chain True Single Phase Clock (AC-TSPC) logic resulting in a latch-free structure. Comparisons with other logic styles show the achievement potential. First simulations for a horizontal redundant adder slice show area and power savings of 40% and 30% compared to complementary Domino logic.

References

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R. H. Krambeck, C. M. Lee and H.-F. S. Law, "High-Speed Compact Circuits with CMOS", Journal of Solid-State Circuits, IEEE, Vol. SC-17, No. 3, June 1982.
[2]
T. E. Williams and M. A. Horowitz, "A Zero-Overhead Self-Timed 160-ns 54-b CMOS Divider", IEEE Journal of Solid-State Circuits, Vol. 26, No. 11, November 1991.
[3]
F. Grassert, D. Timmermann, "Dynamic Single Phase Logic with Self-timed Stages for Power Reduction in Pipeline Circuit Designs", IEEE International Symposium on Circuits and Systems (ISCAS), May 2001, pp. IV 144--147.
[4]
G. Yee, C. Sechen, "Clock-Delayed Domino for Dynamic Circuit Design", IEEE Transactions on VLSI Systems, Vol. 8, No. 4, August 2000.
[5]
S. Kuninobu, T. Nishiyama, H. Edamatsu, T. Taniguchi, N. Takagi, "Design of High Speed MOS Multiplier and Divider Using Redundant Binary Representation", Proc. 8th. Symposium on Computer Arithmetic, New York, 1987, pp. 80--86.
[6]
J. Yuan, I. Karlsson and C. Svensson, "A True Single Phase Clock Dynamic CMOS Circuit Technique", IEEE Journal of Solid-State Circuits, Vol. SC-22, 1987, pp. 899--901.
[7]
F. Grassert, D. Timmermann, "Single-Rail Self-timed Logic Circuits in Synchronous Designs", IEEE MWSCAS Conference, Tulsa, August 2002.

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  1. Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs

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    cover image ACM Conferences
    GLSVLSI '03: Proceedings of the 13th ACM Great Lakes symposium on VLSI
    April 2003
    320 pages
    ISBN:1581136773
    DOI:10.1145/764808
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Publication History

    Published: 28 April 2003

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    Author Tags

    1. dynamic logic
    2. low power
    3. redundant numbers
    4. self-timed logic
    5. single-rail logic

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    GLSVLSI03: Great Lakes Symposium on VLSI 2003
    April 28 - 29, 2003
    D. C., Washington, USA

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