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High-speed processing schemes for summation type and iteration type vector instructions on Hitachi supercomputer S-820 system

Published: 01 June 1988 Publication History

Abstract

The HITACHI supercomputer S-820 system has been developed as Hitachi's top end supercomputer. It is also rated as one of the most powerful supercomputers in the world.
Among the vector instructions which supercomputers support, summation type vector instructions and iteration type vector instructions are not suitable for parallel processing, since elements to be processed are not independent in these instructions. The S-820 employs high-speed processing schemes for summation type vector instructions and iteration type vector instructions; the performance of summation type instructions is enhanced by high-speed post-processing scheme and the performance of iteration type instructions is enhanced by high-speed parallelizing scheme for iteration arithmetic.
Thanks to these schemes, the execution speeds for Kernel 3 and Kernel 4 of the Lawrence Livermore Laboratory's 24 Kernels become 838.7 MFLOPS and 258.5 MFLOPS respectively, and those for Kernel 5, Kernel 6 and Kernel 11 of the Lawrence Livermore Laboratory's 14 Kernels become 114.6 MFLOPS, 111.8 MFLOPS and 98.4 MFLOPS, respectively.

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cover image ACM Conferences
ICS '88: Proceedings of the 2nd international conference on Supercomputing
June 1988
679 pages
ISBN:0897912721
DOI:10.1145/55364
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Association for Computing Machinery

New York, NY, United States

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Published: 01 June 1988

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