research-article

High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States

Authors:

Mehrdad Biglari,

Dietmar FeyAuthors Info & Claims

NANOARCH '18: Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures

Pages 19 - 24

https://doi.org/10.1145/3232195.3232217

Published: 17 July 2018 Publication History

Abstract

ReRAM technologies feature desired properties, e.g. fast switching and high read margin, that make them attractive candidates to be used in non-volatile flip-flops (NVFFs). However, they suffer from limited endurance. Therefore, cell degradation considerations are a necessity for practical deployment in non-volatile processors (NVPs). In this paper, we present two bipolar ReRAM-based NVFFs, Hypnos and Morpheus, with enhanced endurance and energy efficiency. Hypnos reduces the ReRAM electrical stress during set operation while keeping the imposed NVFF area overhead at a minimum. In Morpheus, a write-termination circuit is used to further enhance the ReRAM endurance and energy efficiency at the cost of an affordable area overhead. Moreover, both NVFFs feature run-time tunable resistive states to enable online adjustment of the tradeoff among endurance, retention, energy consumption, and restore success rate (in case of approximate computing). Experimental results demonstrate that Hypnos reduces the ReRAM set degradation by 91%, on average. Moreover, the write-termination mechanism in Morpheus further reduces the remaining degradation by 93%/97% in set/reset operation, on average. The results also demonstrate enhanced energy efficiency in both NVFFs.

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Cited By

S. HNelapati R(2024)Low-power and area-efficient memristor based non-volatile D latch and flip-flop: Design and analysisPLOS ONE10.1371/journal.pone.030007319:3(e0300073)Online publication date: 7-Mar-2024
https://doi.org/10.1371/journal.pone.0300073
Liu XDeng ELuo LJiang LZhang YLiu DPan BKang W(2023)Voltage-Controlled Spin-Orbit-Torque-Based Nonvolatile Flip-Flop Designs for Ultra-Low-Power ApplicationsApplied Sciences10.3390/app13201131613:20(11316)Online publication date: 15-Oct-2023
https://doi.org/10.3390/app132011316
Hosseinzadeh SKlemm MFischer GFey D(2023)Optimizing multi-level ReRAM memory for low latency and low energy consumptionit - Information Technology10.1515/itit-2023-002265:1-2(52-64)Online publication date: 3-May-2023
https://doi.org/10.1515/itit-2023-0022
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Index Terms

High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States
1. Hardware
  1. Emerging technologies
    1. Analysis and design of emerging devices and systems
  2. Very large scale integration design

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cover image ACM Conferences

NANOARCH '18: Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures

July 2018

176 pages

ISBN:9781450358156

DOI:10.1145/3232195

Copyright © 2018 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Publication History

Published: 17 July 2018

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NANOARCH '18

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SIGDA

NANOARCH '18: IEEE/ACM International Symposium on Nanoscale Architectures

July 17 - 19, 2018

Athens, Greece

Acceptance Rates

NANOARCH '18 Paper Acceptance Rate 30 of 56 submissions, 54%;

Overall Acceptance Rate 55 of 87 submissions, 63%

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Cited By

S. HNelapati R(2024)Low-power and area-efficient memristor based non-volatile D latch and flip-flop: Design and analysisPLOS ONE10.1371/journal.pone.030007319:3(e0300073)Online publication date: 7-Mar-2024
https://doi.org/10.1371/journal.pone.0300073
Liu XDeng ELuo LJiang LZhang YLiu DPan BKang W(2023)Voltage-Controlled Spin-Orbit-Torque-Based Nonvolatile Flip-Flop Designs for Ultra-Low-Power ApplicationsApplied Sciences10.3390/app13201131613:20(11316)Online publication date: 15-Oct-2023
https://doi.org/10.3390/app132011316
Hosseinzadeh SKlemm MFischer GFey D(2023)Optimizing multi-level ReRAM memory for low latency and low energy consumptionit - Information Technology10.1515/itit-2023-002265:1-2(52-64)Online publication date: 3-May-2023
https://doi.org/10.1515/itit-2023-0022
Pechmann SMai TVölkel MMahadevaiah MPerez EPerez-Bosch Quesada EReichenbach MWenger CHagelauer A(2021)A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM CellsElectronics10.3390/electronics1005053010:5(530)Online publication date: 24-Feb-2021
https://doi.org/10.3390/electronics10050530
Li YKang WZhao W(2021)Optimized LRU Algorithm for STT-MRAM/SRAM Hybrid Cache Architecture2021 7th International Conference on Computer and Communications (ICCC)10.1109/ICCC54389.2021.9674636(1178-1182)Online publication date: 10-Dec-2021
https://doi.org/10.1109/ICCC54389.2021.9674636
Rziga FMbarek KGhedira SBesbes K(2021)An optimization of a non-volatile latch using memristors for sequential circuit applicationsAnalog Integrated Circuits and Signal Processing10.1007/s10470-021-01863-6Online publication date: 18-May-2021
https://doi.org/10.1007/s10470-021-01863-6
Mbarek KGhedira SRziga FBesbes K(2020)Design and Analysis of Nonvolatile Memristor-based S-R Latch2020 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)10.1109/DTS48731.2020.9196039(1-5)Online publication date: Jun-2020
https://doi.org/10.1109/DTS48731.2020.9196039
Hosseinzadeh SBiglari MFey D(2020)TReMo: A Model for Ternary ReRAM-Based Memories with Adjustable Write-Verification Capabilities2020 23rd Euromicro Conference on Digital System Design (DSD)10.1109/DSD51259.2020.00019(44-48)Online publication date: Aug-2020
https://doi.org/10.1109/DSD51259.2020.00019
Capra MPeloso RMasera GRuo Roch MMartina M(2019)Edge Computing: A Survey On the Hardware Requirements in the Internet of Things WorldFuture Internet10.3390/fi1104010011:4(100)Online publication date: 23-Apr-2019
https://doi.org/10.3390/fi11040100
Biglari MLieske TFey D(2019)Reducing Hibernation Energy and Degradation in Bipolar ReRAM-Based Non-Volatile ProcessorsIEEE Transactions on Nanotechnology10.1109/TNANO.2019.292236318(657-669)Online publication date: 16-Jul-2019
https://dl.acm.org/doi/10.1109/TNANO.2019.2922363
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