research-article

Simplifying HW/SW integration to deploy multiple accelerators for CPU-FPGA heterogeneous platforms

Authors:

Lucas Bragança,

Jeronimo Costa Penha,

Gabriel Coimbra,

Ricardo Ferreira,

José Augusto M. NacifAuthors Info & Claims

SAMOS '18: Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

Pages 97 - 104

https://doi.org/10.1145/3229631.3229651

Published: 15 July 2018 Publication History

Abstract

FPGAS became an interesting option for developing hardware accelerators due to their energy efficiency and recent improvements in CPU-FPGA communication speeds. In order to accelerate the development cycle, FPGA high-level synthesis tools have been developed such as Intel HLS, OpenCL, and OpenSPL. These tools aim to free the designer from having to know all the FPGA low-level details. However, in order to achieve high performance processing, the developer should still understand the details of the deeper system layers. Moreover, OpenCL usually consumes more resources/compile time than a design developed directly in RTL. In this work we propose a novel framework to automatically integrate hardware accelerator cores in a final architecture by generating a HW/SW interface for an Intel CPU-FPGA modern platform. Our goal is to simplify the Intel Open Programmable Acceleration Engine (OPAE) by introducing a novel abstraction layer with a simple stream protocol channel. The experimental results for a set of dataflow benchmarks show a performance of up to 131.7 Gops/s, and a power efficiency of up to 353.7 Gops/W even when we bound the memory bandwidth to 12 GB/s.

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Cited By

Wang YLi BLu LWang JLi RKan H(2023)Hardware-Software Co-design for Deep Neural Network AccelerationService Science10.1007/978-981-99-4402-6_16(221-230)Online publication date: 27-Jul-2023
https://doi.org/10.1007/978-981-99-4402-6_16
Costa Penha JBragança LCanesche MRibeiro DNacif JFerreira R(2023)Gene regulatory accelerators on cloud FPGAConcurrency and Computation: Practice and Experience10.1002/cpe.782235:24Online publication date: 29-May-2023
https://doi.org/10.1002/cpe.7822

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Published In

cover image ACM Other conferences

SAMOS '18: Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

July 2018

263 pages

ISBN:9781450364942

DOI:10.1145/3229631

General Chair:
Trevor Mudge
University of Michigan - Ann Arbor
,
Program Chair:
Dionisios N. Pnevmatikatos
Technical University of Crete and ICS - FORTH, Greece

Copyright © 2018 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 15 July 2018

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SAMOS XVIII

SAMOS XVIII: Architectures, Modeling, and Simulation

July 15 - 19, 2018

Pythagorion, Greece

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Cited By

Wang YLi BLu LWang JLi RKan H(2023)Hardware-Software Co-design for Deep Neural Network AccelerationService Science10.1007/978-981-99-4402-6_16(221-230)Online publication date: 27-Jul-2023
https://doi.org/10.1007/978-981-99-4402-6_16
Costa Penha JBragança LCanesche MRibeiro DNacif JFerreira R(2023)Gene regulatory accelerators on cloud FPGAConcurrency and Computation: Practice and Experience10.1002/cpe.782235:24Online publication date: 29-May-2023
https://doi.org/10.1002/cpe.7822

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