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A model for array-based approximate arithmetic computing with application to multiplier and squarer design

Authors:

Botang Shao,

Peng LiAuthors Info & Claims

ISLPED '14: Proceedings of the 2014 international symposium on Low power electronics and design

Pages 9 - 14

https://doi.org/10.1145/2627369.2627617

Published: 11 August 2014 Publication History

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Abstract

We propose a general model for array-based approximate arithmetic computing to trade off accuracy for significant reduction in energy consumption, which is realized by identifying input signatures for efficient compensation of approximation errors. Under this model, our approximate 16x16 bits fixed-width Booth multiplier consumes 44.96% and 28.33% less energy and area compared with the most accurate fixed-width Booth multiplier. Furthermore, it reduces average error, max error and mean square by 10.46%, 30.77% and 21.26%, respectively, when compared with the best reported approximate design. Using the same approach, significant energy consumption, area and error reduction is achieved for a squarer unit.

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Cited By

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Ellaithy D(2024)Approximate Multiplication and Division Calculation for DSP ApplicationsApplied and Computational Mathematics10.11648/j.acm.20241305.1613:5(178-185)Online publication date: 20-Sep-2024
https://doi.org/10.11648/j.acm.20241305.16
Zhou YLin JWang JWang Z(2018)Approximate Comparator: Design and Analysis2018 IEEE International Workshop on Signal Processing Systems (SiPS)10.1109/SiPS.2018.8598366(1-5)Online publication date: Oct-2018
https://doi.org/10.1109/SiPS.2018.8598366
Xu SGregg D(2017)Bitslice Vectors: A Software Approach to Customizable Data Precision on Processors with SIMD Extensions2017 46th International Conference on Parallel Processing (ICPP)10.1109/ICPP.2017.53(442-451)Online publication date: Aug-2017
https://doi.org/10.1109/ICPP.2017.53
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Index Terms

A model for array-based approximate arithmetic computing with application to multiplier and squarer design
1. Hardware
  1. Integrated circuits
    1. Logic circuits
      1. Arithmetic and datapath circuits
  2. Robustness
    1. Design for manufacturability
      1. Yield and cost modeling
      2. Yield and cost optimization

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Published In

ISLPED '14: Proceedings of the 2014 international symposium on Low power electronics and design

August 2014

398 pages

ISBN:9781450329750

DOI:10.1145/2627369

General Chairs:
Yuan Xie
UCSB, USA
,
Tanay Karnik
Intel, USA
,
Program Chairs:
Muhammad M. Khellah
Intel, USA
,
Renu Mehra
Synopsys, USA

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 11 August 2014

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ISLPED'14: International Symposium on Low Power Electronics and Design

August 11 - 13, 2014

California, La Jolla, USA

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ISLPED '14 Paper Acceptance Rate 63 of 184 submissions, 34%;

Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

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Ellaithy D(2024)Approximate Multiplication and Division Calculation for DSP ApplicationsApplied and Computational Mathematics10.11648/j.acm.20241305.1613:5(178-185)Online publication date: 20-Sep-2024
https://doi.org/10.11648/j.acm.20241305.16
Zhou YLin JWang JWang Z(2018)Approximate Comparator: Design and Analysis2018 IEEE International Workshop on Signal Processing Systems (SiPS)10.1109/SiPS.2018.8598366(1-5)Online publication date: Oct-2018
https://doi.org/10.1109/SiPS.2018.8598366
Xu SGregg D(2017)Bitslice Vectors: A Software Approach to Customizable Data Precision on Processors with SIMD Extensions2017 46th International Conference on Parallel Processing (ICPP)10.1109/ICPP.2017.53(442-451)Online publication date: Aug-2017
https://doi.org/10.1109/ICPP.2017.53
Wang QLi YShao BDey SLi P(2017)Energy efficient parallel neuromorphic architectures with approximate arithmetic on FPGANeurocomputing10.1016/j.neucom.2016.09.071221:C(146-158)Online publication date: 19-Jan-2017
https://dl.acm.org/doi/10.1016/j.neucom.2016.09.071
Kim YZhang YLi P(2015)Energy Efficient Approximate Arithmetic for Error Resilient Neuromorphic ComputingIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2014.236545823:11(2733-2737)Online publication date: Nov-2015
https://doi.org/10.1109/TVLSI.2014.2365458
Shao BLi P(2015)Array-Based Approximate Arithmetic Computing: A General Model and Applications to Multiplier and Squarer DesignIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2015.238883962:4(1081-1090)Online publication date: Apr-2015
https://doi.org/10.1109/TCSI.2015.2388839
Zervakis GXydis STsoumanis KSoudris DPekmestzi K(2015)Hybrid approximate multiplier architectures for improved power-accuracy trade-offs2015 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)10.1109/ISLPED.2015.7273494(79-84)Online publication date: Jul-2015
https://doi.org/10.1109/ISLPED.2015.7273494

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A Review, Classification, and Comparative Evaluation of Approximate Arithmetic Circuits

Efficient semisystolic architectures for finite-field arithmetic

A Novel Signed Array Multiplier

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A Review, Classification, and Comparative Evaluation of Approximate Arithmetic Circuits

Efficient semisystolic architectures for finite-field arithmetic

A Novel Signed Array Multiplier

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