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Memristors for neural branch prediction: a case study in strict latency and write endurance challenges

Published: 14 May 2013 Publication History

Abstract

Memristors offer many potential advantages over more traditional memory-cell technologies, including the potential for extreme densities, and fast read times. Current devices, however, are plagued by problems of yield, and durability. We present a limit study of an aggressive neural network application that has a high update rate and a strict latency requirement, analog neural branch predictor. Of course, traditional analog neural network (ANN) implementations of branch predictors are not built with the idea that the underlying bits are likely to fail due to both manufacturing and wear-out issues. Without some careful precautions, a direct one-to-one replacement will result in poor behavior.
We propose a hybrid system that uses SRAM front-end cache, and a distributed-sum scheme to overcome memristors' limitations. Our design can leverage devices with even modest durability (surviving only hours of continuous switching) to provide a system lasting 5 or more years of continuous operation. In addition, these schemes allow for a fault-tolerant design as well. We find that, while a neural predictor benefits from larger density, current technology parameters do not allow high dense, energy-efficient design. Thus, we discuss a range of plausible memristor characteristics that would; as the technology advances; make them practical for our application.

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    cover image ACM Conferences
    CF '13: Proceedings of the ACM International Conference on Computing Frontiers
    May 2013
    302 pages
    ISBN:9781450320535
    DOI:10.1145/2482767
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    Published: 14 May 2013

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    Author Tags

    1. analog computations
    2. branch prediction
    3. neural networks
    4. reliability

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    May 14 - 16, 2013
    Ischia, Italy

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    CF '13 Paper Acceptance Rate 26 of 49 submissions, 53%;
    Overall Acceptance Rate 273 of 785 submissions, 35%

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