Abstract
This paper addresses the detection improvement of Gate Oxide Short defect using a delay test strategy. To achieve this objective, the concept of detectability interval is first introduced in the context of detection of short defects using Boolean test technique. Then this paradigm is extended to the detection of Gate Oxide Short defects using delay testing. Finally, it is shown that it is possible to significantly improve the detection of this kind of defect.
About the authors
J.-M. Galliere is currently working in the Microelectronic department of the Laboratory of Computer Science, Robotics and Microelectronics of Montpellier (LIRMM) as associate professor. His main research interests concern defect modeling.
LIRMM, 161 rue Ada, 34095 MontpellierCedex 5, France
Florence Azaïs is currently working in the Microelectronics department of the Laboratory of Computer Science, Robotics and Microelectronics of Montpellier (LIRMM) as CNRS researcher. Her main research interests include defect modeling, AMS and RF circuit testing, MEMS testing.
LIRMM, 161 rue Ada, 34095 Montpellier Cedex 5, France
M. Comte is currently working in the Microelectronic department of the Laboratory of Computer Science, Automation and Microelectronics of Montpellier (LIRMM) as associate professor. Her main research interests concern defect modeling and test of mixed-signal and RF integrated circuits.
LIRMM, 161 rue Ada, 34095 Montpellier Cedex 5, France
M. Renovell, IEEE fellow, is currently deputy-Director of LIRMM and Assistant-Director of the National Institute INS2I-CNRS. His main research interests are defect modeling and mixed-signal and RF IC testing.
LIRMM, 161 rue Ada, 34095 Montpellier Cedex 5, France
©2014 Walter de Gruyter Berlin/Boston
