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Simultaneous Timing Driven Tree Surgery in Routing with Machine Learning-based Acceleration

Published: 30 May 2018 Publication History

Abstract

In global routing, both timing and routability are critical criterions to measure the performance of a design. However, these two objectives naturally conflict with each other during routing. In this paper, a tree surgery technique is presented to adjust routing tree topologies in global routing to fix timing. We formulate the problem as a quadratic program(QP), which adjusts routing topologies of all the nets from a global perspective and takes congestion into consideration to trade off timing and routability objectives. We also apply machine learning-based techniques to accelerate our algorithm, which offers a fast and effective way to solve the problem. Experimental results on ICCAD~2015 benchmarks show that our algorithms can achieve 10.12% timing improvement with no significant degradation in routability and wirelength. With machine learning-based acceleration (MLA), our results can be obtained in almost negligible runtime.

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    cover image ACM Conferences
    GLSVLSI '18: Proceedings of the 2018 Great Lakes Symposium on VLSI
    May 2018
    533 pages
    ISBN:9781450357241
    DOI:10.1145/3194554
    Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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    Published: 30 May 2018

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    Author Tags

    1. machine learning acceleration
    2. timing driven routing

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    • the Research Grants Council of the Hong Kong Special Administrative Region China

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    GLSVLSI '18: Great Lakes Symposium on VLSI 2018
    May 23 - 25, 2018
    IL, Chicago, USA

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    GLSVLSI '18 Paper Acceptance Rate 48 of 197 submissions, 24%;
    Overall Acceptance Rate 312 of 1,156 submissions, 27%

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