research-article

Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches

Authors:

Wenqing WuAuthors Info & Claims

ICCAD '12: Proceedings of the International Conference on Computer-Aided Design

Pages 88 - 94

https://doi.org/10.1145/2429384.2429401

Published: 05 November 2012 Publication History

Abstract

Using the spin-transfer torque random access memory (STT-RAM) technology as lower level on-chip caches has been proposed to minimize leakage power consumption and enhance cache capacity at the scaled technologies. However, programming STT-RAM is a stochastic process due to the random thermal fluctuations. Conventional worst-case (corner) design with a fixed write pulse period cannot completely eliminate the write failures but maintain it at a low level by paying high cost in hardware complexity and system performance. In this work, we systematically study the impacts of the stochastic switching of STT-RAM on circuit and cache performance. Two probabilistic design techniques, write-verify-rewrite with adaptive period (WRAP) and verify-one-while-writing (VOW), then are proposed for performance improvement and write failure reduction. Our simulation results show that compared to the result of the conventional design using Hamming Code to correct the write failures, WRAP is write error free while reducing the cache write latency and energy consumption by 40% and 26%, respectively. When an extremely low write failure rate (i.e., 10⁻²²) is allowed, VOW can further boost the reductions on write latency and energy to 52% and 29%, respectively. Furthermore, a hybrid STT-RAM based cache hierarchy taking advantages of probabilistic design techniques is proposed. The novel hierarchy can reduce the write failure rate of STT-RAM cache to 10⁻³⁰, while improving the speed by 6.8% and saving 15% of energy consumption compared to a conventional design with Hamming Code.

References

[1]

"The International Technology Roadmap for Semiconductors," http://www.itrs.net, 2010.

[2]

Y. Chen et al., "Processor caches built using multi-level spin-transfer torque RAM cells," in Int'l Symposium on Low Power Electronics and Design (ISLPED), 2011, pp. 73--78.

Digital Library

[3]

W. Xu et al., "Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT-RAM)," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 19, no. 3, pp. 483--493, 2011.

Digital Library

[4]

E. Ipek et al., "Dynamically replicated memory: building reliable systems from nanoscale resistive memories," in Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems, 2010, pp. 3--14.

Digital Library

[5]

S. Schechter et al., "Use ecp, not ecc, for hard failures in resistive memories," in Proceedings of the 37th Annual International Symposium on Computer Architecture(ISCA), 2010, pp. 141--152.

Digital Library

[6]

H. Sun et al., "Design techniques to improve the device write margin for mram-based cache memory," in GLSVLSI, 2011, pp. 97--102.

Digital Library

[7]

M. Hosomi et al., "A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram," in IEDM, 2005, pp. 459--462.

[8]

T. Kawahara et al., "2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read," IEEE Journal of Solid-State Circuits, vol. 43, no. 1, pp. 109--120, 2008.

[9]

W. Zhao and Y. Cao, "New generation of predictive technology model for sub-45 nm early design exploration," IEEE Transactions on Electron Devices, vol. 53, no. 11, pp. 2816--2823, 2006.

[10]

Y. Zhang et al., "Stt-ram cell design optimization for persistent and non-persistent error rate reduction: A statistical design view," in International Conference on Computer Aided Design (ICCAD), 2011, pp. 471--477.

Digital Library

[11]

X. Wang et al., "Thermal fluctuation effects on spin torque induced switching: Mean and variations," Journal of Applied Physics, vol. 103, no. 3, p. 034507, 2008.

[12]

J. C. Slonczewski, "Currents, torques, and polarization factors in magnetic tunnel junctions," Phys. Rev. B, vol. 71, no. 2, p. 024411, 2005.

[13]

X. Bi et al., "Spintronic memristor based temperature sensor design with cmos current reference," in Design, Automation Test in Europe Conference Exhibition (DATE), 2012, pp. 1301--1306.

[14]

C. Xu et al., "Design implications of memristor-based rram cross-point structures," in Design, Automation Test in Europe Conference Exhibition (DATE), 2011, pp. 1--6.

[15]

C. Bienia, "Benchmarking modern multiprocessors," Ph.D. dissertation, Princeton University, January 2011.

Digital Library

[16]

"Wind River Simics," http://www.windriver.com/products/simics/.

[17]

X. Dong et al., "Circuit and Microarchitecture Evaluation of 3D Stacking Magnetic RAM (MRAM) as a Universal Memory Replacement," in Design Automation Conference (DAC), 2008, pp. 554--559.

Digital Library

[18]

G. Sun et al., "A Novel Architecture of the 3D Stacked MRAM L2 Cache for CMPs," in Int'l Symposium on High Performance Computer Architecture (HPCA), 2009, pp. 239--249.

[19]

P. Zhou et al., "Energy reduction for stt-ram using early write termination," in Proceedings of the International Conference on Computer-Aided Design (ICCAD), 2009, pp. 264--268.

Digital Library

Cited By

Rajpoot JVerma S(2023)Area-Efficient Auto-Write-Terminate Circuit for NV Latch and Logic-In-Memory ApplicationsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2023.324298970:7(2630-2634)Online publication date: Jul-2023
https://doi.org/10.1109/TCSII.2023.3242989
Yang AJiang ZHuang ZZhang ZJiang Y(2023)Double-Ended Superposition Anti-Noise Resistance Monitoring Write Termination Scheme for Reliable Write Operation in STT-MRAMIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2022.322758270:3(1147-1160)Online publication date: Mar-2023
https://doi.org/10.1109/TCSI.2022.3227582
Rajpoot JGupta MVerma S(2023)Enhancing the Reliability of Hybrid MTJ/CMOS Circuits with Auto Write Termination2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)10.1109/IPFA58228.2023.10249113(1-6)Online publication date: 24-Jul-2023
https://doi.org/10.1109/IPFA58228.2023.10249113
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Index Terms

Probabilistic design methodology to improve run-time stability and performance of STT-RAM caches
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory
      2. Static memory

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cover image ACM Conferences

ICCAD '12: Proceedings of the International Conference on Computer-Aided Design

November 2012

781 pages

ISBN:9781450315739

DOI:10.1145/2429384

General Chair:
Alan J. Hu
Univ. of British Columbia, Vancouver, BC, Canada

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 05 November 2012

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ICCAD '12

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ICCAD '12: The International Conference on Computer-Aided Design

November 5 - 8, 2012

California, San Jose

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Rajpoot JVerma S(2023)Area-Efficient Auto-Write-Terminate Circuit for NV Latch and Logic-In-Memory ApplicationsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2023.324298970:7(2630-2634)Online publication date: Jul-2023
https://doi.org/10.1109/TCSII.2023.3242989
Yang AJiang ZHuang ZZhang ZJiang Y(2023)Double-Ended Superposition Anti-Noise Resistance Monitoring Write Termination Scheme for Reliable Write Operation in STT-MRAMIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2022.322758270:3(1147-1160)Online publication date: Mar-2023
https://doi.org/10.1109/TCSI.2022.3227582
Rajpoot JGupta MVerma S(2023)Enhancing the Reliability of Hybrid MTJ/CMOS Circuits with Auto Write Termination2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)10.1109/IPFA58228.2023.10249113(1-6)Online publication date: 24-Jul-2023
https://doi.org/10.1109/IPFA58228.2023.10249113
Nguyen TLee J(2023)Sparse Code With Minimum Hamming Distance of Three for Spin-Torque Transfer Magnetic Random Access MemoryIEEE Access10.1109/ACCESS.2023.332425511(114071-114079)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3324255
Nguyen TLee J(2023)Improving Bit-Error-Rate Performance Using Modulation Coding Techniques for Spin-Torque Transfer Magnetic Random Access MemoryIEEE Access10.1109/ACCESS.2023.326352711(33005-33013)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3263527
Rahbari MFarbeh H(2022)CRP: Conditional Replacement Policy for Reliability Enhancement of STT-MRAM CachesIEEE Transactions on Magnetics10.1109/TMAG.2022.317526958:7(1-13)Online publication date: Jul-2022
https://doi.org/10.1109/TMAG.2022.3175269
Wang QJiang Y(2022)Weighted Error Correcting Code (WECC) for Asymmetric Errors in STT-MRAM2022 Joint MMM-Intermag Conference (INTERMAG)10.1109/INTERMAG39746.2022.9827877(1-5)Online publication date: Jan-2022
https://doi.org/10.1109/INTERMAG39746.2022.9827877
Khan MGhosh S(2021)Comprehensive Study of Security and Privacy of Emerging Non-Volatile MemoriesJournal of Low Power Electronics and Applications10.3390/jlpea1104003611:4(36)Online publication date: 24-Sep-2021
https://doi.org/10.3390/jlpea11040036
Sayed NMao LTahoori M(2021)Dynamic Behavior Predictions for Fast and Efficient Hybrid STT-MRAM CachesACM Journal on Emerging Technologies in Computing Systems10.1145/342313517:1(1-21)Online publication date: 6-Jan-2021
https://dl.acm.org/doi/10.1145/3423135
Choi SAhn HSong BKang SJung S(2021)Self-Referenced Single-Ended Resistance Monitoring Write Termination Scheme for STT-RAM Write Energy ReductionIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2021.306971068:6(2481-2493)Online publication date: Jun-2021
https://doi.org/10.1109/TCSI.2021.3069710
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