Article

Practical low-cost CPL implementations threshold logic functions

Authors:

José M. Quintana,

Maria J. Avedillo,

Raúl Jiménez,

Esther Rodríguez-VillegasAuthors Info & Claims

GLSVLSI '01: Proceedings of the 11th Great Lakes symposium on VLSI

Pages 139 - 144

https://doi.org/10.1145/368122.368903

Published: 01 March 2001 Publication History

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References

[1]

S. Muroga, Threshold Logic & its Applications, Wiley- Inter-science 1971.

Google Scholar

[2]

K.Y. Siu and V.P. Roychowdhury, "On Optimal Depth Threshold Circuits For Multiplication And Related Problems", SIAM J. Discrete Math, vol. 7, no. 2, pp 284-292, 1994.

Digital Library

Google Scholar

[3]

K.Y. Siu, V.P. Roychowdhury and T. Kailath, "Toward Massively Parallel Design of Multipliers", J. of Parallel and Distributed Computing, 24, pp. 86-93, 1995.

Digital Library

Google Scholar

[4]

R. Impagliazzo, R. Paturi and M. E. Saks, "Size-Depth Tradeoffs for Threshold Circuits", SIAM J. Comput., vol. 26, no. 3, pp. 693-707, 1997.

Digital Library

Google Scholar

[5]

C.L. Lee, C-W. Jen: "Bit-sliced median filter design based on majority gate", IEE Proc.-G, vol. 139, No. 1, pp. 63-71, Feb. 1992.

Google Scholar

[6]

C.L. Lee, C-W. Jen, "CMOS Threshold gate and networks for order statistic filtering", IEEE Tr. on Circ. and Syst. -I, vol. 41, No. 6, pp. 453-456, June 1994.

Crossref

Google Scholar

[7]

J.M. Quintana, M.J. Avedillo and A.Rueda, "Hazard-free edge-triggered D flipflop based on Threshold Gates", Elect. Let. vol. 30, no. 17, pp. 1390-1391, Aug. 1994.

Crossref

Google Scholar

[8]

T. Shibata, T. Ohmi, "A functional MOS transistor featuring gate level weighted sum and threshold operations", IEEE J. Solid-State Circ., vol. 39, pp. 1444-1445, 1992.

Google Scholar

[9]

W. Weber, et al., "On the application of the Neuron MOS Transistor Principle for Modern VLSI Design", IEEE Tran. Electron Devices, vol. 43, No. 10, pp. 1700-1708, October 1996.

Crossref

Google Scholar

[10]

J.M. Quintana, M.J. Avedillo, A. Rueda y C. Baena, "Practical Low-Cost CMOS realization of Complex Logic Functions", Proc. of European Conf. on Circuit Theory and Design, ECCTD'95, pp. 51-54.

Google Scholar

[11]

E. Rodriguez, G. Huertas, M.J. Avedillo, J.M. Quintana, and A. Rueda, "A Practical Floating-Gate Muller-C Element Using nMOS Threshold Gates," to appear in the Special Issue on Floating Gate Circuits and Systems, IEEE Trans. on Circuits and Systems -II: Analog and Digital Signal Processing.

Google Scholar

[12]

A.P. Chandrakasan, S. Sheng, and R.W. Brodersen, "Low- Power CMOS Digital Design", IEEE J. Solid-State Circ., vol. 27, pp. 473-483, April 1992.

Crossref

Google Scholar

[13]

C.F. Law, S.S. Rofail, and K.S. Yeo, "A Low-Power Parallel Multiplier Utilizing Pass-Transistor Logic", IEEE J. Solid-State Circ., vol. 34, no. 10, pp. 1395-1399, October 1999.

Crossref

Google Scholar

[14]

K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohi-gashi, A. Shimizu, "A 3.8-ns CMOS Multiplier Using Complementary Pass-Transistor Logic", IEEE J. Solid-State Circ., vol. 25, no. 2, pp. 388-395, April 1990.

Crossref

Google Scholar

[15]

A.P. Chandrakasan and R.W. Brodersen, Low-Power Digital CMOS Design. Norwell, MA: Kluwer, 1995.

Digital Library

Google Scholar

[16]

R. Zimmermann and W. Fichtner, "Low-Power Logic Styles: CMOS Versus Pass-Transistor Logic," IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1079-1090, July 1997.

Crossref

Google Scholar

[17]

C. Mead and L. Conway, Introduction to VLSI Systems, Addison-Wesley, 1980.

Digital Library

Google Scholar

[18]

E. Rodriguez-Villegas, M.J. Avedillo, J.M. Quintana, and A. Rueda, "Threshold Logic Based Adders Using Floating-Gate Circuits", 4th CSCC, 2000 World Multiconference, July 2000.

Google Scholar

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Kulkarni NYang JSeo JVrudhula S(2016)Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-FlopsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.252778324:9(2873-2886)Online publication date: Sep-2016
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Practical low-cost CPL implementations threshold logic functions
1. Hardware

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GLSVLSI '01: Proceedings of the 11th Great Lakes symposium on VLSI

March 2001

152 pages

ISBN:1581133510

DOI:10.1145/368122

Chairmen:
Kaushik Roy
Purdue Univ., West Lafayette, IN
,
Sung-Mo (Steve) Kang
Univ. of California at Santa Cruz
,
Cheng-Kok Koh
Purdue Univ., West Lafayette, IN

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 March 2001

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Kulkarni NYang JSeo JVrudhula S(2016)Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-FlopsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.252778324:9(2873-2886)Online publication date: Sep-2016
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Bai YSun YLin M(2016)Stochastic-based logic circuit synthesis and implementation through large-fanin threshold logic with magnetic tunneling junctions2016 International Conference on Integrated Circuits and Microsystems (ICICM)10.1109/ICAM.2016.7813563(55-60)Online publication date: Nov-2016
https://doi.org/10.1109/ICAM.2016.7813563
Ercan FMuhtaroglu A(2015)Comparative power-delay performance analysis of threshold logic technologies5th International Conference on Energy Aware Computing Systems & Applications10.1109/ICEAC.2015.7352166(1-4)Online publication date: Mar-2015
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Rajendran JManem HKarri RRose G(2012)An Energy-Efficient Memristive Threshold Logic CircuitIEEE Transactions on Computers10.1109/TC.2011.2661:4(474-487)Online publication date: 1-Apr-2012
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Rajendran JManem HKarri RRose GDas SBahar INiemier M(2010)Memristor based programmable threshold logic arrayProceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures10.5555/1835957.1835961(5-10)Online publication date: 17-Jun-2010
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Žaloudek LSekanina L(2008)Transistor-Level Evolution of Digital Circuits Using a Special Circuit SimulatorProceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware10.1007/978-3-540-85857-7_28(320-331)Online publication date: 21-Sep-2008
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Multi-Input Variable-Threshold Circuits for Multi-Valued Logic Functions

Four-valued threshold logic full adder circuit implementations

Novel low-cost and fault-tolerant reversible logic adders

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Multi-Input Variable-Threshold Circuits for Multi-Valued Logic Functions

Four-valued threshold logic full adder circuit implementations

Novel low-cost and fault-tolerant reversible logic adders

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