research-article

Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach

Authors:

Marcelo Mandelli,

Gabriel Marchesan Almeida,

Leandro Moller,

Leandro Soares Indrusiak,

Gilles Sassatelli,

Manfred Glesner,

Fernando MoraesAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 12, Issue 3

Article No.: 75, Pages 1 - 22

https://doi.org/10.1145/2442116.2442125

Published: 08 April 2013 Publication History

Abstract

The mapping of tasks to processing elements of an MPSoC has critical impact on system performance and energy consumption. To cope with complex dynamic behavior of applications, it is common to perform task mapping during runtime so that the utilization of processors and interconnect can be taken into account when deciding the allocation of each task. This paper has two major contributions, one of them targeting the general problem of evaluating dynamic mapping heuristics in NoC-based MPSoCs, and another focusing on the specific problem of finding a task mapping that optimizes energy consumption in those architectures.

References

[1]

Almeida, G. M., Sassatelli, G., Benoit, P., Saint-Jean, N., Varyani, S., Torres, L., and Robert, M. 2009. An adaptive message passing MPSoC framework. International Journal of Reconfigurable Computing.

[2]

Carara, E., Oliveira, R., Calazans, N., and Moraes, F. 2009. HeMPS - A framework for NoC-based MPSoC generation. In Proceedings of the International Symposium on Circuits and Systems (ISCAS). 1345--1348.

[3]

Carvalho, E., Marcon, C., Calazans, N., and Moraes, F. 2009. Evaluation of static and dynamic task mapping algorithms in NoC-based MPSoCs. In Proceedings of the International Conference on System-on-chip (SoC). 87--90.

Digital Library

[4]

Chou, C-L. and Marculescu, R. 2007. Incremental run-time application mapping for homogeneous NoCs with multiple voltage Levels. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). 161--166.

Digital Library

[5]

Chou, C-L. and Marculescu, R. 2008. User-aware dynamic task allocation in networks-on-chip. In Proceedings of the Design, Automation and Test in Europe (DATE). 1232--1237.

Digital Library

[6]

Chou, C-L. and Marculescu, R. 2010. Run-time task allocation considering user behavior in embedded multiprocessor networks-on-chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, 1, 78--91.

Digital Library

[7]

Faruque, M. A., Krist, R., and Henkel, J. 2008. ADAM: Run-time agent-based distributed application mapping for on-chip communication. In Proceedings of the Design Automation Conference(DAC). 760--765.

Digital Library

[8]

HA, S. 2008. Model-based programming environment of embedded software for MPSoC. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC). 330--335.

Digital Library

[9]

Hölzenspies, P. K. F., Hurink, J. L., Kuper, J., and Smit, G. J. M. 2008. Run-time spatial mapping of streaming applications to a heterogeneous multi-processor system-on-chip (MPSoC). In Proceedings of the Design, Automation and Test in Europe (DATE). 212--217.

Digital Library

[10]

Hosseinabady, M., and Nunez-Yanes, J. 2009. Run-time resource management in fault-tolerant network on reconfigurable chips. In Proceedings of the Field Programmable Logic and Applications (FPL). 574--577.

[11]

Hu, J., and Marculescu, R. 2005. Energy- and performance-aware mapping for regular NoC architectures. IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems 24, 4, 551--562.

Digital Library

[12]

Indrusiak, L. S., Thuy, A., and Glesner, M. 2007. Executable system-level specification models containing UML-based behavioral patterns. In Proceedings of the Design, Automation and Test in Europe (DATE), 301--306.

Digital Library

[13]

Indrusiak, L. S., Ost, L., Moraes, F. G., Maatta, S., Nurmi, J., Moller, L., and Glesner, M. 2010. Evaluating the impact of communication latency on applications running over on-chip multiprocessing platforms: A layered approach. In Proceedings of the International Conference on Industrial Informatics (INDIN). 148--153.

[14]

Indrusiak, L. S., and Santos, O. 2011. Fast and Accurate Transaction-Level Model of a Wormhole Network-on-Chip with Priority Preemptive Virtual Channel Arbitration. In Design, Automation and Test in Europe (DATE). 1--6.

[15]

Jalier, C., Lattard, D., Jerraya, A. A., Sassatellli, G., Benoit, P., and Torres, L. 2010. Heterogeneous versus homogeneous MPSoC approaches for a mobile LTE modem. In Proceedings of the Design, Automation and Test in Europe (DATE). 184--189.

Digital Library

[16]

Kahng, A., Li, B., Peh, L., and Samadi, K. 2009. ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration. In Proceedings of the Design, Automation and Test in Europe (DATE). 423--428.

Digital Library

[17]

Kangas, T., Kukkala, P., Orsila, H., Salminen, E., Hännikäinen, M., Hämäläinen, T., Riihimäki, J., and Kuusilinna, K. 2006. UML-based multiprocessor SoC design framework. ACM Transactions on Embedded Computing Systems 5, 2, 281--320.

Digital Library

[18]

Lee, E. A. and Neuendorffer, S. 2004. Actor-oriented models for codesign: Balancing re-use and performance. Formal Methods and Models for System Design. Kluwer Academic Publishers, Norwell, MA. 33--56.

Digital Library

[19]

Lee, H. G., Ogras, U. Y., Marculescu, R., and Chang, N. 2006. Design space exploration and prototyping for on-chip multimedia applications. In Proceedings of the Design Automation Conference (DAC). 1--6.

Digital Library

[20]

Lee S. E. and Bagherzadeh, N. 2009. A high level power model for Network-on-Chip (NoC) router. Computers & Electrical Engineering 35, 6, 837--845.

Digital Library

[21]

LI, K. 2010. A random-walk-based dynamic tree evolution algorithm with exponential speed of convergence to optimality on regular networks. In Proceedings of the Conference Frontier of Computer Science and Technology (FCST). 80--85.

Digital Library

[22]

Lu, S., Lu, C., and Hsiung., P. 2010. Congestion- and energy-aware run-time mapping for tile-based network-on-chip architecture. In Proceedings of the Frontier Computing, Theory, Technologies and Applications (FCTTA), 300--305.

[23]

Määttä, S., Indrusiak, L. S., Ost, L., Möller, L., Nurmi, J., Glesner, M., and Moraes, F. 2008. Validation of executable application models mapped onto network-on-chip platforms. In Proceedings of the IEEE Symposium on Industrial Embedded Systems (SIES). 118--125.

[24]

Määttä, S., Indrusiak, L. S., Ost, L., Möller, L., Nurmi, J., Glesner, M., and Moraes, F. 2009. Characterising embedded applications using a UML profile. In Proceedings of the International Conference on System-on-Chip (SoC). 172--175.

Digital Library

[25]

Määttä, S., Indrusiak, L. S., Ost, L., Möller, L., Nurmi, J., Glesner, M., and Moraes, F. 2010. Joint validation of application models and multi-abstraction network-on-chip platforms. International Journal of Embedded and Real-Time Communication Systems (IJERTCS) 1, 1, 86--101.

Digital Library

[26]

Mandelli, M., Ost, L., Carara, E., Guindani, G., Gouvea, T., Medeiros, G., and Moraes, F. 2011. Energy-aware dynamic task mapping for NoC-based MPSoCs. In Proceedings of the International Symposium on Circuits and Systems (ISCAS). 1676--1679.

[27]

Mandelli, M., Amory, A., Ost, L., and Moraes, F. 2011b. Multi-task dynamic mapping onto NoC-based MPSoCs. In Proceedings of the Symposium on Integrated Circuits and Systems Design (SBCCI). 191--196.

Digital Library

[28]

Marcon, C., Moreno, E. I., Calazans, N. L. V., and Moraes, F. 2008. Comparison of network-on-chip mapping algorithms targeting low energy consumption. IET Computers and Digital Techniques 2, 6, 471--482.

[29]

Marculescu, R., Ogras, U., Peh, L., Jerger, N., and Hoskote, Y. 2009. Out-standing research problems in NoC design: System, microarchitecture, and circuit perspectives. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28, 1, 3--21.

Digital Library

[30]

Milojevic, D., Montperrus, L., and Verkest, D. 2009. Power dissipation of the network-on-chip in multi-processor system-on-chip dedicated for video coding applications. Journal of Signal Processing Systems 57, 2, 139--153.

Digital Library

[31]

Mischkalla, F., He, D, and Mueller, W. 2010. Closing the gap between UML-based modeling, simulation and synthesis of combined HW/SW systems. In Proceedings of the Design, Automation and Test in Europe (DATE'). 1201--1206.

Digital Library

[32]

Molnos, A., Ambrose, J. A., Nelson, A., Stefan, R., Cotofana, S., and Goossens, K. A 2010. Composable, energy-managed, real-time MPSOC platform. In Proceedings of the Optimization of Electrical and Electronic Equipment (OPTIM). 870--876.

[33]

Ngouanga, A., Sassatelli, G., Torres, L., Gil, T., Soares, A., and Susin, A. 2006. A contextual re-sources use: proof of concept through the APACHES platform. In Proceedings of the Design and Diagnostics of Electronic Circuits and Systems (DDECS). 42--47.

Digital Library

[34]

Ost, L., Indrusiak, L. S., Guindani, G., Reinbrecht, C., Raupp, T., and F. Moraes. 2009. A high abstraction, high accuracy power estimation model for networks-on-chip. In Proceedings of the Symposium on Integrated Circuits and Systems Design (SBCCI). 193--198.

Digital Library

[35]

Ost, L., Guindani, G., Indrusiak, L. S., Määttä, S., and Moraes, F. 2011. Exploring NoC-based MPSoC design space with power estimation models. IEEE Design and Test of Computers 28, 2, 16--29.

Digital Library

[36]

Omg. 2011. Object Management Group: UML Profile for MARTE: Modeling and Analysis of Real-Time Embedded Systems.http://www.omg.org/spec/MARTE/1.0/PDF/.

[37]

Pimentel, A. D., Thompson, M., Polstra, S., and Erbas, C. 2008. Calibration of abstract performance models for system-level design space exploration. J. Sig. Proc. Syst. 50, 2, 99--114.

Digital Library

[38]

Schranzhofer, A., Chen, J.-J., and Thiele, L. 2010. Dynamic power-aware mapping of applications onto heterogeneous MPSoC platforms. IEEE Trans. Indust. Info. 6, 4, 692--707.

[39]

Smit, L. T., Hurink, J. L., and Smit, G. J. M. 2005. Run-time mapping of applications to a heterogeneous SoC. In Proceedings of the International Symposium on System-on-Chip (SoC). 78--81.

[40]

Singh, A. K., Srikanthan, T., Kumar, A., and Jigang, W. 2010. Communication-aware heuristics for run-time task mapping on NoC-based MPSoC platforms. J. Syst. Archite. 56, 7, 242--255.

Digital Library

[41]

Weichslgartner, A., Wildermann, S., and Teich, J. 2011. Dynamic decentralized mapping of tree-structured applications on NoC architectures. In Proceedings of the Networks on Chip (NoC). 201--209.

Digital Library

[42]

Wildermann, S., Ziermann, T., and Teich, J. 2009. Run time mapping of adaptive applications onto homogeneous NoC-based reconfigurable architectures. In Proceedings of the Field-Programmable Technology (FPT). 514--517.

[43]

Ye, T., Benini, L., and De Micheli, G. 2002. Analysis of power consumption on switch fabrics in network routers. In Proceedings of the Design Automation and Conference (DAC). 524--529.

Digital Library

Cited By

Paul S(2024)An Adaptive Strategy for Dynamic Resource Allocation and Scheduling for Multitasking NoC based Multicore Systems2024 28th International Symposium on VLSI Design and Test (VDAT)10.1109/VDAT63601.2024.10705675(1-6)Online publication date: 1-Sep-2024
https://doi.org/10.1109/VDAT63601.2024.10705675
Bhowmik B(2023)ANN-Based Performance Prediction in MoCsArtificial Intelligence10.1007/978-3-031-22485-0_13(133-144)Online publication date: 1-Jan-2023
https://doi.org/10.1007/978-3-031-22485-0_13
Paul SChatterjee NGhosal PDiguet J(2021)A Hybrid Adaptive Strategy for Task Allocation and Scheduling for Multi-applications on NoC-based Multicore Systems with Resource Sharing2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE51398.2021.9474079(1663-1666)Online publication date: 1-Feb-2021
https://doi.org/10.23919/DATE51398.2021.9474079
Show More Cited By

Index Terms

Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach
1. Computer systems organization
2. Hardware
  1. Hardware validation

Recommendations

Multi-task dynamic mapping onto NoC-based MPSoCs
SBCCI '11: Proceedings of the 24th symposium on Integrated circuits and systems design

Task mapping defines the best placement of a given task in the MPSoC, according to some criteria, as energy or Manhattan distance minimization. The ITRS roadmap forecast in a near future MPSoCs with hundreds of processing elements (PEs). Therefore, ...
Exploring dynamic mapping impact on NoC-based MPSoCs performance using a model-based framework
SBCCI '11: Proceedings of the 24th symposium on Integrated circuits and systems design

The power evaluation of NoC-based MPSoCs is an important and a time-consuming process. Mapping tasks onto processing elements (PEs) has a critical impact on system performance, as well as power dissipation. To cope with complex dynamic behavior of ...
Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs
RSP '07: Proceedings of the 18th IEEE/IFIP International Workshop on Rapid System Prototyping

Multiprocessor Systems-on-Chip (MPSoCs) is a trend in VLSI design, since they minimize the "design crisis” (gap between silicon technology and actual SoC design capacity) and reduce the time to market. Important issues in MPSoC design are the ...

Comments

Information & Contributors

Information

Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 12, Issue 3

March 2013

463 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/2442116

Issue’s Table of Contents

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Journal Family

ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 08 April 2013

Accepted: 01 December 2011

Revised: 01 August 2011

Received: 01 March 2011

Published in TECS Volume 12, Issue 3

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

28
Total Citations
View Citations
541
Total Downloads

Downloads (Last 12 months)5
Downloads (Last 6 weeks)1

Reflects downloads up to 24 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Paul S(2024)An Adaptive Strategy for Dynamic Resource Allocation and Scheduling for Multitasking NoC based Multicore Systems2024 28th International Symposium on VLSI Design and Test (VDAT)10.1109/VDAT63601.2024.10705675(1-6)Online publication date: 1-Sep-2024
https://doi.org/10.1109/VDAT63601.2024.10705675
Bhowmik B(2023)ANN-Based Performance Prediction in MoCsArtificial Intelligence10.1007/978-3-031-22485-0_13(133-144)Online publication date: 1-Jan-2023
https://doi.org/10.1007/978-3-031-22485-0_13
Paul SChatterjee NGhosal PDiguet J(2021)A Hybrid Adaptive Strategy for Task Allocation and Scheduling for Multi-applications on NoC-based Multicore Systems with Resource Sharing2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE51398.2021.9474079(1663-1666)Online publication date: 1-Feb-2021
https://doi.org/10.23919/DATE51398.2021.9474079
Sharma DKirischian L(2021)A Decision-Making Method Providing Sustainability to FPGA-Based SoCs by Run-Time Structural Adaptation to Mode of Operation, Power Budget, and Die Temperature VariationsInternational Journal of Reconfigurable Computing10.1155/2021/55129382021Online publication date: 1-Jan-2021
https://dl.acm.org/doi/10.1155/2021/5512938
Jayshree Seetharaman GPati D(2021)Energy consumption and performance comparison of DE optimization and PSO-based IP-core mapping technique for 2D and 3D network-on-chipSemiconductor Science and Technology10.1088/1361-6641/ac038c36:8(085015)Online publication date: 14-Jul-2021
https://doi.org/10.1088/1361-6641/ac038c
Dahir NKarkar APalesi MMak TYakovlev A(2021)Power density aware application mapping in mesh-based network-on-chip architectureIntegration, the VLSI Journal10.1016/j.vlsi.2021.08.00881:C(342-353)Online publication date: 1-Nov-2021
https://dl.acm.org/doi/10.1016/j.vlsi.2021.08.008
Fang JZhao HZhang Jshi J(2021)A Heterogeneous Multi-core Network-on-Chip Mapping Optimization AlgorithmAlgorithms and Architectures for Parallel Processing10.1007/978-3-030-95384-3_24(370-384)Online publication date: 3-Dec-2021
https://dl.acm.org/doi/10.1007/978-3-030-95384-3_24
Richthammer VRieß MBestler JSlomka FGlaß MDi Natale GFummi F(2020)Design space exploration for model-based communication systemsProceedings of the 23rd Conference on Design, Automation and Test in Europe10.5555/3408352.3408478(556-561)Online publication date: 9-Mar-2020
https://dl.acm.org/doi/10.5555/3408352.3408478
Richthammer VRies MBestler JSlomka FGlas M(2020)Design Space Exploration for Model-based Communication Systems2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE48585.2020.9116508(556-561)Online publication date: Mar-2020
https://doi.org/10.23919/DATE48585.2020.9116508
Ruaro MJantsch AMoraes F(2019)Self-Adaptive QoS Management of Computation and Communication Resources in Many-Core SoCsACM Transactions on Embedded Computing Systems10.1145/332875518:4(1-21)Online publication date: 10-Jun-2019
https://dl.acm.org/doi/10.1145/3328755
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Article

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Issue’s Table of Contents