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Physical design exploration of 3D tree-based FPGA architecture

Authors:

Vinod Pangracious,

Emna Amouri,

Habib Mehrez,

Zied MarrakchiAuthors Info & Claims

GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI

Pages 335 - 336

https://doi.org/10.1145/2483028.2483130

Published: 02 May 2013 Publication History

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Abstract

An innovative 3D physical design exploration methodology for Tree-based FPGA architecture is presented in this paper. In a Tree-based FPGA architecture, the interconnects are arranged in a multidimensional network with the logic unites and switch blocks placed at different levels, using a Butterfly-Fat Tree network topology. A 3D physical design exploration methodology leverage on Through Silicon Via (TSVs) using a horizontal break-point to re-distribute the Tree interconnects into multiple stacked active silicon layers proposed in this paper.

References

[1]

J. L. Ayala, A. Sridhar, V. Pangracious, D. Atienza, and Y. Leblebici. Through Silicon Via-Based Grid for Thermal Control in 3D Chips. NanoNet Springer, pages 90--98, June 2009.

Crossref

Google Scholar

[2]

V. Betrz, A. Marquardt, and J. Rose. A New Packing Placement and Routing Tool for FPGA Research. Inter Workshop on FPGA., 15(5):213--222, Nov 1997.

Digital Library

Google Scholar

[3]

V. Betz and J. Rose. Circuit Design, Transistor Sizing and Wire Layout of FPGA Interconnect. IEEE Custom Integrated Circuit Conference, 1999.

Google Scholar

[4]

I. Kuon, A. Egier, and J. Rose. Design Layout and Verification of FPGA using Automated Tool. FPGA 2005, pages 215--226.

Digital Library

Google Scholar

[5]

Z. Marrakchi, H. Mrabet, E. Amouri, and H. Mehrez. Efficient Tree Topology for FPGA Interconnect Network. ACM GLSVLSI., pages 321--326, 2006.

Digital Library

Google Scholar

[6]

Z. Marrakchi, H. Mrabet, U. Farooq, and H. Mehrez. FPGA Interconnect Topologies Exploration. Inter J of Reconfigurable Comput., 15(5):795--825, Nov 2009.

Digital Library

Google Scholar

[7]

A. Rahman, S. Das, A. Chandrakasan, and R. Reif. Wiring Requirments and Three-Dimensional Integration of Field Programmable Gate Arrays. SLIP ACM, March 2001.

Digital Library

Google Scholar

[8]

K. Siozios, A. Bartzas, and D. Soudris. Architecture Level Exploration of Alternative schmes Targeting 3D FPGAs: A Software Supported Methodology. Intern Journal of Reconfigurable Computing, 2011.

Google Scholar

Cited By

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Dash RMajumdar APangracious VTuruk ARisco-Martin J(2018)ATAR: An Adaptive Thermal-Aware Routing Algorithm for 3-D Network-on-Chip SystemsIEEE Transactions on Components, Packaging and Manufacturing Technology10.1109/TCPMT.2018.28421028:12(2122-2129)Online publication date: Dec-2018
https://doi.org/10.1109/TCPMT.2018.2842102
Pangracious VMehrez HMarakchi Z(2013)Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology2013 IEEE International 3D Systems Integration Conference (3DIC)10.1109/3DIC.2013.6702342(1-8)Online publication date: Oct-2013
https://doi.org/10.1109/3DIC.2013.6702342

Index Terms

Physical design exploration of 3D tree-based FPGA architecture
1. Hardware
  1. Emerging technologies

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Information

Published In

GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI

May 2013

368 pages

ISBN:9781450320320

DOI:10.1145/2483028

General Chair:
Jose L. Ayala
Complutense University of Madrid, Spain
,
Program Chairs:
Alex Jones
University of Pittsburgh, USA
,
Patrick Madden
Binghamton University, USA
,
Publications Chair:
Ayse K. Coskun
Boston University, USA

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 May 2013

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GLSVLSI'13

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SIGDA

GLSVLSI'13: Great Lakes Symposium on VLSI 2013

May 2 - 3, 2013

Paris, France

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GLSVLSI '13 Paper Acceptance Rate 76 of 238 submissions, 32%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Dash RMajumdar APangracious VTuruk ARisco-Martin J(2018)ATAR: An Adaptive Thermal-Aware Routing Algorithm for 3-D Network-on-Chip SystemsIEEE Transactions on Components, Packaging and Manufacturing Technology10.1109/TCPMT.2018.28421028:12(2122-2129)Online publication date: Dec-2018
https://doi.org/10.1109/TCPMT.2018.2842102
Pangracious VMehrez HMarakchi Z(2013)Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology2013 IEEE International 3D Systems Integration Conference (3DIC)10.1109/3DIC.2013.6702342(1-8)Online publication date: Oct-2013
https://doi.org/10.1109/3DIC.2013.6702342

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Novel Three-Dimensional Embedded FPGA Technology and Achitecture

Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA

Clock Tree synthesis for TSV-based 3D IC designs