research-article

Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores

Authors:

Emre Kultursay,

Karthik Swaminathan,

Vinay Saripalli,

Vijaykrishnan Narayanan,

Mahmut T. Kandemir,

Suman DattaAuthors Info & Claims

CODES+ISSS '12: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Pages 245 - 254

https://doi.org/10.1145/2380445.2380487

Published: 07 October 2012 Publication History

Abstract

Device level heterogeneity promises high energy efficiency over a larger range of voltages than a single device technology alone can provide. In this paper, starting from device models, we first present ground-up modeling of CMOS and TFET cores, and verify this model against existing processors. Using our core models, we construct a 32-core TFET-CMOS heterogeneous multicore. We then show that it is a very challenging task to identify the ideal runtime configuration to use in such a heterogeneous multicore, which includes finding the best number/type of cores to activate and the corresponding voltages/frequencies to select for these cores. In order to effectively utilize this heterogeneous processor, we propose a novel automated runtime scheme. Our scheme is designed to automatically improve the performance of applications running on heterogeneous CMOS-TFET multicores operating under a fixed power budget, without requiring any effort from the application programmer or the user. Our scheme combines heterogeneous thread-to-core mapping, dynamic work partitioning, and dynamic power partitioning to identify energy efficient operating points. With simulations we show that our runtime scheme can enable a CMOS-TFET multicore to serve a diversity of workloads with high energy efficiency and achieve 21% average speedup over the best performing equivalent homogeneous multicore.

References

[1]

S. Borkar. Thousand Core Chips: A Technology Perspective. In DAC, 2007.

Digital Library

[2]

H. Wei et al. Scaling with Design Constraints: Predicting the Future of Big Chips. IEEE Micro, 2011.

Digital Library

[3]

D.K Mohata et al. Demonstration of MOSFET-Like On-Current Performance in Arsenide/Antimonide Tunnel FETs with Staggered Hetero-junctions for 300mV Logic Applications. In IEDM, 2011.

[4]

V. Saripalli et al. An Energy-Efficient Heterogeneous CMP based on Hybrid TFET-CMOS cores. In DAC, 2011.

Digital Library

[5]

International Technology Roadmap for Semiconductors. 2011.

[6]

B. Wheeler. Calxeda Spins 4W Server-on-a-Chip. In Microprocessor Report, Nov 2011.

[7]

V. Aslot et al. SPECOMP: A New Benchmark Suite for Measuring Parallel Computer Performance. In International Workshop on OpenMP Applications and Tools, 2001.

Digital Library

[8]

S. Mookerjea et al. Experimental Demonstration of 100nm Channel Length In0.53Ga0.47As-based Vertical Inter-band Tunnel Field Effect Transistors (TFETs) for Ultra Low-Power Logic and SRAM Applications. In IEDM, 2009.

[9]

R. Gandhi et al. Vertical Si-Nanowire n -Type Tunneling FETs With Low Subthreshold Swing ( ≤ 50mV/decade ) at Room Temperature. IEDM, 2011.

[10]

D.K. Mohata et al. Self-aligned Gate NanoPillar In0.53Ga0.47As Vertical Tunnel Transistor. In DRC, 2011.

[11]

M. Luisier and G. Klimeck. Performance Comparisons of Tunneling Field-Effect Transistors Made of InSb, Carbon, and GaSb-InAs Broken Gap Heterostructures. In IEDM, 2009.

[12]

U. E. Avci et al. Comparison of Performance, Switching Energy and Process Variations for the TFET and MOSFET in Logic. In VLSIT, 2011.

[13]

Intel Corporation. Intel 22nm 3-D Tri-Gate Transistor Technology, May 2011.

[14]

M. LaPedus. TSMC to make FinFETs in 450-mm fab, February 2011.

[15]

C.C. Wu et al. High Performance 22/20nm FinFET CMOS Devices with Advanced high-K/metal Gate Scheme. In IEDM, 2010.

[16]

Synopsys. TCAD Sentaurus Device Manual, Release: C-2009.06, 2009.

[17]

Wei Zhao and Yu Cao. New Generation of Predictive Technology Model for Sub-45nm Design Exploration. In ISQED, 2006.

Digital Library

[18]

Intel Corporation. Intel Atom Processor Z5xx Series - Datasheet, June 2010.

[19]

Xilinx. Xilinx Power Tools Tutorial: Spartan and Virtex 6 FPGAs.

[20]

A. Sinha and A.P. Chandrakasan. JouleTrack-a Web based tool for software energy profiling. In DAC, 2001.

Digital Library

[21]

S. Datta et al. Ultrahigh-Speed 0.5 V Supply Voltage In0.7Ga0.3As Quantum-Well Transistors on Silicon Substrate. IEEE Electron Device Letters, 28(8):685 --687, Aug. 2007.

[22]

V. Saripalli et al. Variation-tolerant Ultra Low-Power Heterojunction Tunnel FET SRAM Design. Nanoscale Architectures, 2011.

Digital Library

[23]

C. D. Polychronopoulos and D. J. Kuck. Guided self-scheduling: A practical scheduling scheme for parallel supercomputers. IEEE Trans. Comput., 36(12), December 1987.

Digital Library

[24]

P. S. Magnusson et al. Simics: A Full System Simulation Platform. Computer, 35, February 2002.

Digital Library

[25]

W. Kim et al. System Level Analysis of Fast, Per-Core DVFS using On-Chip Switching Regulators. In ISCA, 2008.

[26]

OpenMP. OpenMP, http://www.openmp.org.

[27]

R. Kumar et al. Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction. In MICRO, 2003.

Digital Library

[28]

T. Y. Morad et al. Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors. IEEE Comput. Archit. Lett., 5, January 2006.

Digital Library

[29]

E. Ipek et al. Core Fusion: Accommodating Software Diversity in Chip Multiprocessors. In ISCA, 2007.

Digital Library

[30]

M. A. Suleman et al. Accelerating Critical Section Execution with Asymmetric Multi-core Architectures. In ASPLOS, 2009.

Digital Library

[31]

E. S. Chung et al. Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs? In MICRO, 2010.

Digital Library

[32]

Ganesh Venkatesh et al. Conservation Cores: Reducing the Energy of Mature Computations. In ASPLOS, 2010.

Digital Library

[33]

E. Humenay et al. Impact of Process Variations on Multicore Performance Symmetry. In DATE, 2007.

Digital Library

[34]

R. Teodorescu and J. Torrellas. Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors. In ISCA, 2008.

Digital Library

[35]

U. R. Karpuzcu et al. The BubbleWrap many-core: popping cores for sequential acceleration. In MICRO, 2009.

Digital Library

[36]

K. Swaminathan et al. Improving Energy Efficiency of Multi-Threaded Applications using Heterogeneous CMOS-TFET Multicores. In ISLPED, 2011.

Digital Library

[37]

S. Balakrishnan et al. The Impact of Performance Asymmetry in Emerging Multicore Architectures. In ISCA, 2005.

Digital Library

[38]

M. Bhadauria et al. Accomodating Diversity in CMPs with Heterogeneous Frequencies. In HiPEAC, 2009.

Digital Library

[39]

C-K. Luk et al. Qilin: Exploiting Parallelism on Heterogeneous Multiprocessors with Adaptive Mapping. In MICRO, 2009.

Digital Library

[40]

R. Kumar et al. Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance. In ISCA, 2004.

Digital Library

[41]

M. D. Hill and M. R. Marty. Amdahl's Law in the Multicore Era. Computer, 41, July 2008.

Digital Library

Cited By

Chowdhury JMahapatra KSarkar ADas JKloes A(2024)Design and performance investigation of tunnel-FET based energy efficient approximate and accurate adders targeted towards low power IoT nodesPhysica Scripta10.1088/1402-4896/ad881d99:11(115035)Online publication date: 30-Oct-2024
https://doi.org/10.1088/1402-4896/ad881d
Kim HAmarnath ABagherzadeh JTalati NDreslinski R(2021)A Survey Describing Beyond Si Transistors and Exploring Their Implications for Future ProcessorsACM Journal on Emerging Technologies in Computing Systems10.1145/345314317:3(1-44)Online publication date: 30-Jun-2021
https://dl.acm.org/doi/10.1145/3453143
Hossain MSavidis I(2019)Reusing Leakage Current for Improved Energy Efficiency of Multi-Voltage Systems2019 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2019.8702425(1-5)Online publication date: May-2019
https://doi.org/10.1109/ISCAS.2019.8702425
Show More Cited By

Index Terms

Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Heterogeneous (hybrid) systems
2. Hardware
  1. Communication hardware, interfaces and storage

Recommendations

Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores
ISLPED '11: Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design

Energy-Delay-Product-aware DVFS is a widely-used technique that improves energy efficiency by dynamically adjusting the frequencies of cores. Further, for multithreaded applications, barrier-aware DVFS is a method that can dynamically tune the ...
Heterogeneous parallel_for Template for CPU---GPU Chips

Heterogeneous processors, comprising CPU cores and a GPU, are the de facto standard in desktop and mobile platforms. In many cases it is worthwhile to exploit both the CPU and GPU simultaneously. However, the workload distribution poses a challenge when ...
Steep-Slope Devices: From Dark to Dim Silicon

Although the superior subthreshold characteristics of steep-slope devices can help power up more cores, researchers still need CMOS technology to accelerate sequential applications, because it can reach higher frequencies. Device-level heterogeneous ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

CODES+ISSS '12: Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

October 2012

596 pages

ISBN:9781450314268

DOI:10.1145/2380445

General Chairs:
Ahmed Jerraya
CEA
,
Luca Carloni
Columbia University
,
Program Chairs:
Naehyuck Chang
Seoul National University, Korea
,
Franco Fummi
University of Verona, Italy

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 07 October 2012

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

ESWEEK'12

Sponsor:

ESWEEK'12: Eighth Embedded System Week

October 7 - 12, 2012

Tampere, Finland

Acceptance Rates

CODES+ISSS '12 Paper Acceptance Rate 48 of 163 submissions, 29%;

Overall Acceptance Rate 280 of 864 submissions, 32%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

29
Total Citations
View Citations
308
Total Downloads

Downloads (Last 12 months)3
Downloads (Last 6 weeks)1

Reflects downloads up to 06 Jan 2025

Other Metrics

View Author Metrics

Citations

Cited By

Chowdhury JMahapatra KSarkar ADas JKloes A(2024)Design and performance investigation of tunnel-FET based energy efficient approximate and accurate adders targeted towards low power IoT nodesPhysica Scripta10.1088/1402-4896/ad881d99:11(115035)Online publication date: 30-Oct-2024
https://doi.org/10.1088/1402-4896/ad881d
Kim HAmarnath ABagherzadeh JTalati NDreslinski R(2021)A Survey Describing Beyond Si Transistors and Exploring Their Implications for Future ProcessorsACM Journal on Emerging Technologies in Computing Systems10.1145/345314317:3(1-44)Online publication date: 30-Jun-2021
https://dl.acm.org/doi/10.1145/3453143
Hossain MSavidis I(2019)Reusing Leakage Current for Improved Energy Efficiency of Multi-Voltage Systems2019 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2019.8702425(1-5)Online publication date: May-2019
https://doi.org/10.1109/ISCAS.2019.8702425
Gupta UAyoub RKishinevsky MKadjo DSoundararajan NTursun UOgras U(2018)Dynamic Power Budgeting for Mobile Systems Running Graphics WorkloadsIEEE Transactions on Multi-Scale Computing Systems10.1109/TMSCS.2017.26834874:1(30-40)Online publication date: 1-Jan-2018
https://doi.org/10.1109/TMSCS.2017.2683487
Gopireddy BSkarlatos DZhu WTorrellas J(2018)HetCoreProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00072(802-815)Online publication date: 2-Jun-2018
https://dl.acm.org/doi/10.1109/ISCA.2018.00072
Pagani SChen JShafique MHenkel JPagani SChen JShafique MHenkel J(2018)Background and Related WorkAdvanced Techniques for Power, Energy, and Thermal Management for Clustered Manycores10.1007/978-3-319-77479-4_2(23-34)Online publication date: 27-Apr-2018
https://doi.org/10.1007/978-3-319-77479-4_2
Pagani SChen JShafique MHenkel JPagani SChen JShafique MHenkel J(2018)IntroductionAdvanced Techniques for Power, Energy, and Thermal Management for Clustered Manycores10.1007/978-3-319-77479-4_1(1-22)Online publication date: 27-Apr-2018
https://doi.org/10.1007/978-3-319-77479-4_1
Yang LLiu WJiang WLi MChen PSha E(2017)FoToNoC: A Folded Torus-Like Network-on-Chip Based Many-Core Systems-on-Chip in the Dark Silicon EraIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2016.264366928:7(1905-1918)Online publication date: 10-Jun-2017
https://dl.acm.org/doi/10.1109/TPDS.2016.2643669
Pagani SShafique MHenkel J(2017)Design Space Exploration and Run-Time Adaptation for Multi-core Resource Management Under Performance and Power ConstraintsHandbook of Hardware/Software Codesign10.1007/978-94-017-7358-4_11-1(1-32)Online publication date: 8-Apr-2017
https://doi.org/10.1007/978-94-017-7358-4_11-1
Pagani SShafique MHenkel J(2017)Design Space Exploration and Run-Time Adaptation for Multicore Resource Management Under Performance and Power ConstraintsHandbook of Hardware/Software Codesign10.1007/978-94-017-7267-9_11(301-332)Online publication date: 27-Sep-2017
https://doi.org/10.1007/978-94-017-7267-9_11
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents