research-article

Multi retention level STT-RAM cache designs with a dynamic refresh scheme

Authors:

Hai (Helen) Li,

Zhong-Liang Ong,

Wenqing WuAuthors Info & Claims

MICRO-44: Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

Pages 329 - 338

https://doi.org/10.1145/2155620.2155659

Published: 03 December 2011 Publication History

Abstract

Spin-transfer torque random access memory (STT-RAM) has received increasing attention because of its attractive features: good scalability, zero standby power, non-volatility and radiation hardness. The use of STT-RAM technology in the last level on-chip caches has been proposed as it minimizes cache leakage power with technology scaling down. Furthermore, the cell area of STT-RAM is only 1/9 ~ 1/3 that of SRAM. This allows for a much larger cache with the same die footprint, improving overall system performance through reducing cache misses. However, deploying STT-RAM technology in L1 caches is challenging because of the long and power-consuming write operations. In this paper, we propose both L1 and lower level cache designs that use STT-RAM. In particular, our designs use STT-RAM cells with various data retention time and write performances, made possible by different magnetic tunneling junction (MTJ) designs. For the fast STT-RAM bits with reduced data retention time, a counter controlled dynamic refresh scheme is proposed to maintain the data validity. Our dynamic scheme saves more than 80% refresh energy compared to the simple refresh scheme proposed in previous works. A L1 cache built with ultra low retention STT-RAM coupled with our proposed dynamic refresh scheme can achieve 9.2% in performance improvement, and saves up to 30% of the total energy when compared to one that uses traditional SRAM. For lower level caches with relative large cache capacity, we propose a data migration scheme that moves data between portions of the cache with different retention characteristics so as to maximize the performance and power benefits. Our experiments show that on the average, our proposed multi retention level STT-RAM cache reduces 30 ~ 70% of the total energy compared to previous works, while improving IPC performance for both 2-level and 3-level cache hierarchy.

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Cited By

Bagchi ADharamjeet Rishabh OSuri MPanda P(2024)POEM: Performance Optimization and Endurance Management for Non-volatile CachesACM Transactions on Design Automation of Electronic Systems10.1145/365345229:5(1-36)Online publication date: 27-Mar-2024
https://dl.acm.org/doi/10.1145/3653452
Karunakar SAtkade MPoptani AKalayappan RChandran S(2024)CASH: Criticality-Aware Split Hybrid L1 Data CacheProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658716(50-56)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3658716
Gajaria DAdegbija TGomez K(2024)CHIME: Energy-Efficient STT-RAM-Based Concurrent Hierarchical In-Memory Processing2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP)10.1109/ASAP61560.2024.00053(228-236)Online publication date: 24-Jul-2024
https://doi.org/10.1109/ASAP61560.2024.00053
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Index Terms

Multi retention level STT-RAM cache designs with a dynamic refresh scheme
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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Published In

cover image ACM Conferences

MICRO-44: Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture

December 2011

519 pages

ISBN:9781450310536

DOI:10.1145/2155620

Conference Chair:
Carlo Galuzzi
Technische Universiteit Delft, The Netherlands
,
General Chair:
Luigi Carro
Universidade Federal do Rio Grande do Sul, Brasil
,
Program Chairs:
Andreas Moshovos
University of Toronto, Canada
,
Milos Prvulovic
Georgia Institute of Technology, United States

Copyright © 2011 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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IEEE
ACM: Association for Computing Machinery
UFRGS: Universidade Federal do Rio Grande do Sul
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
IEEE-CS: Computer Society

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 December 2011

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MICRO-44: The 44th Annual IEEE/ACM International Symposium on Microarchitecture

December 3 - 7, 2011

Porto Alegre, Brazil

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Cited By

Bagchi ADharamjeet Rishabh OSuri MPanda P(2024)POEM: Performance Optimization and Endurance Management for Non-volatile CachesACM Transactions on Design Automation of Electronic Systems10.1145/365345229:5(1-36)Online publication date: 27-Mar-2024
https://dl.acm.org/doi/10.1145/3653452
Karunakar SAtkade MPoptani AKalayappan RChandran S(2024)CASH: Criticality-Aware Split Hybrid L1 Data CacheProceedings of the Great Lakes Symposium on VLSI 202410.1145/3649476.3658716(50-56)Online publication date: 12-Jun-2024
https://dl.acm.org/doi/10.1145/3649476.3658716
Gajaria DAdegbija TGomez K(2024)CHIME: Energy-Efficient STT-RAM-Based Concurrent Hierarchical In-Memory Processing2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP)10.1109/ASAP61560.2024.00053(228-236)Online publication date: 24-Jul-2024
https://doi.org/10.1109/ASAP61560.2024.00053
Lai JCai JChu J(2023)A congestion-aware hybrid SRAM and STT-RAM buffer design for network-on-chip routerIEICE Electronics Express10.1587/elex.19.2022007820:2(20220078-20220078)Online publication date: 25-Jan-2023
https://doi.org/10.1587/elex.19.20220078
Singh SSurana NPrasad KJain PMekie JAwasthi M(2023)HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache HierarchyACM Transactions on Architecture and Code Optimization10.1145/357283920:2(1-20)Online publication date: 1-Mar-2023
https://dl.acm.org/doi/10.1145/3572839
Manohar SKapoor H(2023)CAPMIG: Coherence-Aware Block Placement and Migration in Multiretention STT-RAM CachesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.317524242:2(411-422)Online publication date: Feb-2023
https://doi.org/10.1109/TCAD.2022.3175242
Zhao YUllah SSahoo SKumar A(2023) NvMISC : Toward an FPGA-Based Emulation Platform for RISC-V and Nonvolatile Memories IEEE Embedded Systems Letters10.1109/LES.2023.329920215:4(170-173)Online publication date: Dec-2023
https://doi.org/10.1109/LES.2023.3299202
Agarwal SChakraborty SSjälander M(2023)Architecting Selective Refresh based Multi-Retention Cache for Heterogeneous System (ARMOUR)2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247878(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247878
Badri SSaini MGoel N(2023)Efficient placement and migration policies for an STT-RAM based hybrid L1 cache for intermittently powered systemsDesign Automation for Embedded Systems10.1007/s10617-023-09272-w27:4(303-331)Online publication date: 5-May-2023
https://doi.org/10.1007/s10617-023-09272-w
Inci AIsgenc MMarculescu D(2023)Efficient Deep Learning Using Non-volatile Memory Technology in GPU ArchitecturesEmbedded Machine Learning for Cyber-Physical, IoT, and Edge Computing10.1007/978-3-031-19568-6_8(225-252)Online publication date: 1-Oct-2023
https://doi.org/10.1007/978-3-031-19568-6_8
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