poster

Low-latency modular packet header parser for FPGA

Authors:

Viktor Pus,

Lukas Kekely,

Jan KorenekAuthors Info & Claims

ANCS '12: Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems

Pages 77 - 78

https://doi.org/10.1145/2396556.2396571

Published: 29 October 2012 Publication History

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Abstract

Packet parsing is the basic operation performed at all points of the network infrastructure. Modern networks impose challenging requirements on the performance and configurability of packet parsing modules, however the high-speed parsers often use very large chip area. We propose novel architecture of pipelined packet parser, which in addition to high throughput (over 100 Gb/s) offers also low latency. Moreover, the latency to throughput ratio can be finely tuned to fit the particular application.

Reference

[1]

M. Attig and G. Brebner. 400 gb/s programmable packet parsing on a single fpga. In Architectures for Networking and Communications Systems (ANCS), 2011 Seventh ACM/IEEE Symposium on, pages 12--23, oct. 2011.

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Sun YGuo Z(2023)The Design of a Dynamic Configurable Packet Parser Based on FPGAMicromachines10.3390/mi1408156014:8(1560)Online publication date: 5-Aug-2023
https://doi.org/10.3390/mi14081560
Young AMiniskar NLiu FBlokland WVetter J(2023)Adrastea: An Efficient FPGA Design Environment for Heterogeneous Scientific Computing and Machine LearningAccelerating Science and Engineering Discoveries Through Integrated Research Infrastructure for Experiment, Big Data, Modeling and Simulation10.1007/978-3-031-23606-8_14(227-243)Online publication date: 18-Jan-2023
https://doi.org/10.1007/978-3-031-23606-8_14
Duong QTrinh QDao DTrung-Nguyen (2021)A Bufferless Non-exact Matching Hardware Accelerator for Processing Large Non-uniform Stream DataIndustrial Networks and Intelligent Systems10.1007/978-3-030-77424-0_20(245-258)Online publication date: 28-May-2021
https://doi.org/10.1007/978-3-030-77424-0_20
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Index Terms

Low-latency modular packet header parser for FPGA
1. Hardware
  1. Very large scale integration design
    1. Application-specific VLSI designs
      1. Application specific processors

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Information

Published In

ANCS '12: Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems

October 2012

270 pages

ISBN:9781450316859

DOI:10.1145/2396556

General Chair:
Tilman Wolf
University of Massachusetts Amherst, USA
,
Program Chairs:
Andrew W. Moore
University of Cambridge, UK
,
Viktor Prasanna
University of Southern California, USA

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 29 October 2012

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Poster

Conference

ANCS '12

Sponsor:

ANCS '12: Symposium on Architecture for Networking and Communications Systems

October 29 - 30, 2012

Texas, Austin, USA

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Overall Acceptance Rate 88 of 314 submissions, 28%

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Cited By

View all

Sun YGuo Z(2023)The Design of a Dynamic Configurable Packet Parser Based on FPGAMicromachines10.3390/mi1408156014:8(1560)Online publication date: 5-Aug-2023
https://doi.org/10.3390/mi14081560
Young AMiniskar NLiu FBlokland WVetter J(2023)Adrastea: An Efficient FPGA Design Environment for Heterogeneous Scientific Computing and Machine LearningAccelerating Science and Engineering Discoveries Through Integrated Research Infrastructure for Experiment, Big Data, Modeling and Simulation10.1007/978-3-031-23606-8_14(227-243)Online publication date: 18-Jan-2023
https://doi.org/10.1007/978-3-031-23606-8_14
Duong QTrinh QDao DTrung-Nguyen (2021)A Bufferless Non-exact Matching Hardware Accelerator for Processing Large Non-uniform Stream DataIndustrial Networks and Intelligent Systems10.1007/978-3-030-77424-0_20(245-258)Online publication date: 28-May-2021
https://doi.org/10.1007/978-3-030-77424-0_20
Cao ZZhang HLi JWen MZhang C(2019)A Fast Approach for Generating Efficient Parsers on FPGAsSymmetry10.3390/sym1110126511:10(1265)Online publication date: 10-Oct-2019
https://doi.org/10.3390/sym11101265
Orosz PTothfalusi TVarga P(2019)FPGA-Assisted DPI Systems: 100 Gbit/s and BeyondIEEE Communications Surveys & Tutorials10.1109/COMST.2018.287619621:2(2015-2040)Online publication date: Oct-2020
https://doi.org/10.1109/COMST.2018.2876196
Santiago da Silva JBoyer FLanglois JAnderson JBazargan K(2018)P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAsProceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3174243.3174270(147-152)Online publication date: 15-Feb-2018
https://dl.acm.org/doi/10.1145/3174243.3174270
Cabal JBenáček PKekely LKekely MPuš VKořenek JAnderson JBazargan K(2018)Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed ThroughputProceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3174243.3174250(249-258)Online publication date: 15-Feb-2018
https://dl.acm.org/doi/10.1145/3174243.3174250
Talasila PKakrambe MRai ASanty SGoveas NDeshpande B(2018)BITS DarshiniProceedings of the 19th International Conference on Distributed Computing and Networking10.1145/3154273.3154316(1-10)Online publication date: 4-Jan-2018
https://dl.acm.org/doi/10.1145/3154273.3154316
Jyothi VAddepalli SKarri R(2018)DPFEE: A High Performance Scalable Pre-Processor for Network Security SystemsIEEE Transactions on Multi-Scale Computing Systems10.1109/TMSCS.2017.27653244:1(55-68)Online publication date: 1-Jan-2018
https://doi.org/10.1109/TMSCS.2017.2765324
Benacek PPu VKubatova H(2016)P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)10.1109/FCCM.2016.46(148-155)Online publication date: May-2016
https://doi.org/10.1109/FCCM.2016.46
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