research-article

Input and transistor reordering for NBTI and HCI reduction in complex CMOS gates

Authors:

Farshad Firouzi,

Mehdi B. TahooriAuthors Info & Claims

GLSVLSI '12: Proceedings of the great lakes symposium on VLSI

Pages 201 - 206

https://doi.org/10.1145/2206781.2206829

Published: 03 May 2012 Publication History

Abstract

As CMOS feature size scales to the nanometer regime, transistor aging mostly due to Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI), has emerged as a major reliability concern. Threshold voltage shift causes the circuit to fail, once the post-aging delay exceeds the timing constraint. In this paper, we investigate the stacking effect of transistors on aging and propose a novel input/transistor reordering approach to alleviate the effect of NBTI and HCI during the active mode operation of the circuit. According to the results, the circuit failing due to aging effect is postponed by increasing the operational lifetime for ISCAS benchmarks by 23.6%, in average, while it has a negligible effect on delay, area, and power compared to the original cell input ordering.

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Cited By

Singh KKalra S(2021)A Comprehensive Assessment of Current Trends in Negative Bias Temperature Instability (NBTI) Deterioration2021 7th International Conference on Signal Processing and Communication (ICSC)10.1109/ICSC53193.2021.9673357(271-276)Online publication date: 25-Nov-2021
https://doi.org/10.1109/ICSC53193.2021.9673357
Tasoulas ZAnagnostopoulos I(2020)Kernel-Based Resource Allocation for Improving GPU Throughput While Minimizing the Activity Divergence of SMsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2019.293324567:2(428-440)Online publication date: Feb-2020
https://doi.org/10.1109/TCSI.2019.2933245
Gomez AChampac V(2019)An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging EffectsJournal of Electronic Testing: Theory and Applications10.1007/s10836-019-05772-535:1(87-100)Online publication date: 1-Feb-2019
https://dl.acm.org/doi/10.1007/s10836-019-05772-5
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Index Terms

Input and transistor reordering for NBTI and HCI reduction in complex CMOS gates
1. Hardware
  1. Hardware test
  2. Robustness

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cover image ACM Conferences

GLSVLSI '12: Proceedings of the great lakes symposium on VLSI

May 2012

388 pages

ISBN:9781450312448

DOI:10.1145/2206781

General Chairs:
Erik Brunvard
University of Utah, USA
,
Ken Stevens
University of Utah, USA
,
Program Chairs:
Joseph R. Cavallaro
Rice University, USA
,
Tong Zhang
Rensselaer Polytechnic Institute, USA

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 03 May 2012

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GLSVLSI '12: Great Lakes Symposium on VLSI 2012

May 3 - 4, 2012

Utah, Salt Lake City, USA

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Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Singh KKalra S(2021)A Comprehensive Assessment of Current Trends in Negative Bias Temperature Instability (NBTI) Deterioration2021 7th International Conference on Signal Processing and Communication (ICSC)10.1109/ICSC53193.2021.9673357(271-276)Online publication date: 25-Nov-2021
https://doi.org/10.1109/ICSC53193.2021.9673357
Tasoulas ZAnagnostopoulos I(2020)Kernel-Based Resource Allocation for Improving GPU Throughput While Minimizing the Activity Divergence of SMsIEEE Transactions on Circuits and Systems I: Regular Papers10.1109/TCSI.2019.293324567:2(428-440)Online publication date: Feb-2020
https://doi.org/10.1109/TCSI.2019.2933245
Gomez AChampac V(2019)An Efficient Metric-Guided Gate Sizing Methodology for Guardband Reduction Under Process Variations and Aging EffectsJournal of Electronic Testing: Theory and Applications10.1007/s10836-019-05772-535:1(87-100)Online publication date: 1-Feb-2019
https://dl.acm.org/doi/10.1007/s10836-019-05772-5
Lee HShafique MAl Faruque M(2018)Aging-Aware Workload Management on Embedded GPU Under Process VariationIEEE Transactions on Computers10.1109/TC.2018.278990467:7(920-933)Online publication date: 1-Jul-2018
https://dl.acm.org/doi/10.1109/TC.2018.2789904
Lee HShafique MAl Faruque M(2017)Low-overhead Aging-aware Resource Management on Embedded GPUsProceedings of the 54th Annual Design Automation Conference 201710.1145/3061639.3062277(1-6)Online publication date: 18-Jun-2017
https://dl.acm.org/doi/10.1145/3061639.3062277
Ghane MZarandi H(2016)Gate Merging: An NBTI Mitigation Method to Eliminate Critical Internal Nodes in Digital Circuits2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)10.1109/PDP.2016.90(786-791)Online publication date: Feb-2016
https://doi.org/10.1109/PDP.2016.90
Chun JChen C(2016)Transistor and pin reordering for leakage reduction in CMOS circuitsMicroelectronics Journal10.1016/j.mejo.2016.04.00553(25-34)Online publication date: Jul-2016
https://doi.org/10.1016/j.mejo.2016.04.005
Oboril FTahoori M(2015)Cross-layer approaches for an aging-aware design of nanoscale microprocessors: Dissertation summary: IEEE TTTC E.J. McCluskey doctoral thesis award competition finalist2015 IEEE International Test Conference (ITC)10.1109/TEST.2015.7342422(1-10)Online publication date: Oct-2015
https://doi.org/10.1109/TEST.2015.7342422
Oboril FEbrahimi MKiamehr STahoori M(2015)Cross-layer resilient system design flow2015 IEEE International Symposium on Circuits and Systems (ISCAS)10.1109/ISCAS.2015.7169182(2457-2460)Online publication date: May-2015
https://doi.org/10.1109/ISCAS.2015.7169182
Oboril FTahoori M(2014)Aging-Aware Design of Microprocessor Instruction PipelinesIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2014.229833333:5(704-716)Online publication date: May-2014
https://doi.org/10.1109/TCAD.2014.2298333
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