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High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies

Authors:

Mohamed W. Allam,

Mohab H. Anis,

Mohamed I. ElmasryAuthors Info & Claims

ISLPED '00: Proceedings of the 2000 international symposium on Low power electronics and design

Pages 155 - 160

https://doi.org/10.1145/344166.344562

Published: 01 August 2000 Publication History

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Abstract

A new high-speed Domino circuit, called HS-Domino is developed. HS-Domino resolves the trade-off between performance and noise margins in conventional CD-Domino logic while dissipating low dynamic power with minimal area overhead. A dual-threshold (MTCMOS) implementation of HS-Domino and DDCVS logic is also devised. This implementation achieves low leakage values during standby, while maintaining high performance and low dynamic power during the active mode.

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Gupta TPandey APandey D(2023)Influence of Gate Oxide and Subthreshold Leakage in Domino Using Si Nano-MaterialsSilicon10.1007/s12633-023-02555-815:16(6901-6910)Online publication date: 16-Jun-2023
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High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies
1. Hardware

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ISLPED '00: Proceedings of the 2000 international symposium on Low power electronics and design

August 2000

313 pages

ISBN:1581131909

DOI:10.1145/344166

Editors:
David Blaauw
Motorola, Inc., Austin, TX
,
Christian Enz
CSEM, Maladière, Switzerland
,
Thad Gabara
Lucent Technologies
,
Enrico Macii
Politenico di Torino, Turin, Italy

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Published: 01 August 2000

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ISLPED00: International Symposium on Low Power Electronic Design

July 25 - 27, 2000

Rapallo, Italy

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Zhou RTabrizchi SMorsali MRoohi AAngizi S(2023)P-PIM: A Parallel Processing-in-DRAM Framework Enabling Row Hammer Protection2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137204(1-6)Online publication date: Apr-2023
https://doi.org/10.23919/DATE56975.2023.10137204
Gupta TPandey APandey D(2023)Influence of Gate Oxide and Subthreshold Leakage in Domino Using Si Nano-MaterialsSilicon10.1007/s12633-023-02555-815:16(6901-6910)Online publication date: 16-Jun-2023
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Lakshmaiah DKoteswara Rao LSatya Narayana IRajeshwari BVenu IAnil Kumar BGoyal SIslam S(2022)A Novel Feedforward Offset Cancellation Limiting Amplifier in Radio FrequenciesCognitive Computing Models in Communication Systems10.1002/9781119865605.ch13(189-197)Online publication date: 7-Oct-2022
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Singhal SMehra A(2021)Gated Clock and Revised Keeper (GCRK) Domino Logic Design in 16 nm CMOS TechnologyIETE Journal of Research10.1080/03772063.2021.187526969:3(1686-1693)Online publication date: 28-Jan-2021
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Sharroush SAbdalla Y(2021)Optimum sizing of the sleep transistor in MTCMOS technologyAEU - International Journal of Electronics and Communications10.1016/j.aeue.2021.153882138(153882)Online publication date: Aug-2021
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Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies

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Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies

Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling

ESD design strategies for high-speed digital and RF circuits in deeply scaled silicon technologies

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