Article

Hardware-software bipartitioning for dynamically reconfigurable systems

Authors:

Daler N. Rakhmatov,

Sarma B. K. VrudhulaAuthors Info & Claims

CODES '02: Proceedings of the tenth international symposium on Hardware/software codesign

Pages 145 - 150

https://doi.org/10.1145/774789.774819

Published: 06 May 2002 Publication History

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Abstract

The main unique feature of dynamically reconfigurable systems is the ability to time-share the same reconfigurable hardware resources. However, the energy-delay cost associated with reconfiguration must be accounted for during hardware-software partitioning. We propose a method for mapping nodes of an application control flow graph either to software or reconfigurable hardware, explicitly targeting minimization of the energy-delay cost due to both computation and configuration. The addressed problems are energy-delay product minimization, delay-constrained energy minimization, and energy-constrained delay minimization. We show how these problems can be tackled by using network flow techniques, after transforming the original control flow graph into an equivalent network. If there are no constraints, as in the case of the energy-delay product minimization, we are able to generate an optimal solution in polynomial time.

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Cited By

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Ghasemi MHeidari SKim YLamb AWu CVrudhula S(2021)Energy-Efficient Mapping for a Network of DNN Models at the Edge2021 IEEE International Conference on Smart Computing (SMARTCOMP)10.1109/SMARTCOMP52413.2021.00024(25-30)Online publication date: Aug-2021
https://doi.org/10.1109/SMARTCOMP52413.2021.00024
Purnaprajna MReformat MPedrycz W(2018)Genetic algorithms for hardware-software partitioning and optimal resource allocationJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2006.10.01253:7(339-354)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1016/j.sysarc.2006.10.012
Shoa AShirani S(2018)Run-time reconfigurable systems for digital signal processing applicationsJournal of VLSI Signal Processing Systems10.1007/s11265-005-4841-x39:3(213-235)Online publication date: 26-Dec-2018
https://dl.acm.org/doi/10.1007/s11265-005-4841-x
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Index Terms

Hardware-software bipartitioning for dynamically reconfigurable systems
1. Hardware
  1. Communication hardware, interfaces and storage
2. Mathematics of computing
  1. Discrete mathematics
    1. Graph theory

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Published In

CODES '02: Proceedings of the tenth international symposium on Hardware/software codesign

May 2002

232 pages

ISBN:1581135424

DOI:10.1145/774789

General Chairs:
Joerg Henkel
C & C Research Labs, NEC
,
Xiaobo Sharon Hu
University of Notre Dame
,
Program Chairs:
Rajesh Gupta
University of California, Irvine
,
Sri Parameswaran
University of New South Wales, Australia

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 06 May 2002

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CODES02: 10th International Symposium on Hardware/Software Codesign

May 6 - 8, 2002

Colorado, Estes Park

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Ghasemi MHeidari SKim YLamb AWu CVrudhula S(2021)Energy-Efficient Mapping for a Network of DNN Models at the Edge2021 IEEE International Conference on Smart Computing (SMARTCOMP)10.1109/SMARTCOMP52413.2021.00024(25-30)Online publication date: Aug-2021
https://doi.org/10.1109/SMARTCOMP52413.2021.00024
Purnaprajna MReformat MPedrycz W(2018)Genetic algorithms for hardware-software partitioning and optimal resource allocationJournal of Systems Architecture: the EUROMICRO Journal10.1016/j.sysarc.2006.10.01253:7(339-354)Online publication date: 29-Dec-2018
https://dl.acm.org/doi/10.1016/j.sysarc.2006.10.012
Shoa AShirani S(2018)Run-time reconfigurable systems for digital signal processing applicationsJournal of VLSI Signal Processing Systems10.1007/s11265-005-4841-x39:3(213-235)Online publication date: 26-Dec-2018
https://dl.acm.org/doi/10.1007/s11265-005-4841-x
Shannon LChow P(2011)Leveraging reconfigurability in the hardware/software codesign processACM Transactions on Reconfigurable Technology and Systems10.1145/2000832.20008404:3(1-27)Online publication date: 22-Aug-2011
https://dl.acm.org/doi/10.1145/2000832.2000840
Sigdel KThompson MGaluzzi CPimentel ABertels K(2009)rSesame - A generic system-level runtime simulation framework for reconfigurable architectures2009 International Conference on Field-Programmable Technology10.1109/FPT.2009.5377630(460-464)Online publication date: Dec-2009
https://doi.org/10.1109/FPT.2009.5377630
Hsiung PLin CLiao C(2008)PerfectoACM Transactions on Reconfigurable Technology and Systems (TRETS)10.1145/1391732.13917371:3(1-30)Online publication date: 19-Sep-2008
https://dl.acm.org/doi/10.1145/1391732.1391737
Stitt GVahid FHa SChoi KDutt NTeich J(2007)Thread warpingProceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis10.1145/1289816.1289841(93-98)Online publication date: 30-Sep-2007
https://dl.acm.org/doi/10.1145/1289816.1289841
Antola ASantambrogio MFracassi MGotti PSandionigi C(2007)A Novel Hardware/Software Codesign Methodology Based on Dynamic Reconfiguration with Impulse C and Codeveloper2007 3rd Southern Conference on Programmable Logic10.1109/SPL.2007.371754(221-224)Online publication date: Feb-2007
https://doi.org/10.1109/SPL.2007.371754
Hsiung PHuang CLiao C(2006)Perfecto: A Systemc-Based Performance Evaluation Framework for Dynamically Partially Reconfigurable Systems2006 International Conference on Field Programmable Logic and Applications10.1109/FPL.2006.311213(1-6)Online publication date: Aug-2006
https://doi.org/10.1109/FPL.2006.311213
Miramond BDelosme J(2005)Design Space Exploration for Dynamically Reconfigurable ArchitecturesProceedings of the conference on Design, Automation and Test in Europe - Volume 110.1109/DATE.2005.118(366-371)Online publication date: 7-Mar-2005
https://dl.acm.org/doi/10.1109/DATE.2005.118
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Hardware and software infrastructure to implement many-core systems in modern FPGAs

Virtualizable hardware/software design infrastructure for dynamically partially reconfigurable systems

Hardware Resource Virtualization for Dynamically Partially Reconfigurable Systems

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