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Experimental Validation of a Faithful Binary Circuit Model

Authors:

Robert Najvirt,

Michael Hofbauer,

Matthias Függer,

Kurt SchweigerAuthors Info & Claims

GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSI

Pages 355 - 360

https://doi.org/10.1145/2742060.2742081

Published: 20 May 2015 Publication History

Abstract

Fast digital timing simulations based on continuous-time, digital-value circuit models are an attractive and heavily used alternative to analog simulations. Models based on analytic delay formulas are particularly interesting here, as they also facilitate formal verification and delay bound synthesis of complex circuits. Recently, Függer et al. (arXiv:1406.2544 [cs.OH]) proposed a circuit model based on so-called involution channels. It is the first binary circuit model that realistically captures solvability of short-pulse filtration, a non-trivial glitch propagation problem related to building one-shot inertial delays.

In this work, we address the question of whether involution channels also accurately model the delay of real circuits. Using both Spice simulations and physical measurements, we confirm that modeling an inverter chain by involution channels accurately describes reality. We also demonstrate that transitions in vanishing pulse trains are accurately predicted by the involution model. For our Spice simulations, we used both UMC-90 and UMC-65 technology, with varying supply voltages from nominal down to near sub-threshold range. The measurements were performed on a special-purpose UMC-90 ASIC that combines an inverter chain with low-intrusive high-speed on-chip analog amplifiers.

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M. Függer, R. Najvirt, T. Nowak, and U. Schmid, "Faithful glitch propagation in binary circuit models," arXiv:1406.2544, 2014. (appears in Proc. DATE'15).

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Cited By

Ferdowsi ASchmid USalzmann J(2023)Accurate Hybrid Delay Models for Dynamic Timing Analysis2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323646(1-9)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323646
Ferdowsi AFügger MSalzmann JSchmid U(2023)A Hybrid Delay Model for Interconnected Multi-Input Gates2023 26th Euromicro Conference on Digital System Design (DSD)10.1109/DSD60849.2023.00060(381-390)Online publication date: 6-Sep-2023
https://doi.org/10.1109/DSD60849.2023.00060
Fugger MNajvirt RNowak TSchmid U(2020)A Faithful Binary Circuit ModelIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.293774839:10(2784-2797)Online publication date: Oct-2020
https://doi.org/10.1109/TCAD.2019.2937748
Show More Cited By

Index Terms

Experimental Validation of a Faithful Binary Circuit Model
1. Hardware
  1. Integrated circuits

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Published In

cover image ACM Conferences

GLSVLSI '15: Proceedings of the 25th edition on Great Lakes Symposium on VLSI

May 2015

418 pages

ISBN:9781450334747

DOI:10.1145/2742060

General Chairs:
Alex K. Jones
University of Pittsburgh, USA
,
Hai (Helen) Li
University of Pittsburgh, USA
,
Program Chairs:
Ayse K. Coskun
Boston University, USA
,
Martin Margala
University of Massachusetts, Lowell, USA

Copyright © 2015 Owner/Author.

Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the Owner/Author.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 20 May 2015

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Austrian Science Fund

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GLSVLSI '15

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SIGDA

GLSVLSI '15: Great Lakes Symposium on VLSI 2015

May 20 - 22, 2015

Pennsylvania, Pittsburgh, USA

Acceptance Rates

GLSVLSI '15 Paper Acceptance Rate 41 of 148 submissions, 28%;

Overall Acceptance Rate 312 of 1,156 submissions, 27%

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Cited By

Ferdowsi ASchmid USalzmann J(2023)Accurate Hybrid Delay Models for Dynamic Timing Analysis2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323646(1-9)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323646
Ferdowsi AFügger MSalzmann JSchmid U(2023)A Hybrid Delay Model for Interconnected Multi-Input Gates2023 26th Euromicro Conference on Digital System Design (DSD)10.1109/DSD60849.2023.00060(381-390)Online publication date: 6-Sep-2023
https://doi.org/10.1109/DSD60849.2023.00060
Fugger MNajvirt RNowak TSchmid U(2020)A Faithful Binary Circuit ModelIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.293774839:10(2784-2797)Online publication date: Oct-2020
https://doi.org/10.1109/TCAD.2019.2937748
Ohlinger DMaier JFugger MSchmid U(2019)The Involution Tool for Accurate Digital Timingand Power Analysis2019 29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)10.1109/PATMOS.2019.8862165(1-8)Online publication date: Jul-2019
https://doi.org/10.1109/PATMOS.2019.8862165
Fugger MMaier JNajvirt RNowak TSchmid U(2018)A faithful binary circuit model with adversarial noise2018 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2018.8342219(1327-1332)Online publication date: Mar-2018
https://doi.org/10.23919/DATE.2018.8342219

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